Výsledky vyhledávání - "Venkata Chaitanya Krishna Chekuri"

Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs

Autor: Jinwoo Kim, Nael Mizanur Rahman, Hakki Mert Torun, Majid Ahadi Dolatsara, Venkata Chaitanya Krishna Chekuri, Sung Kyu Lim, Madhavan Swaminathan, Saibal Mukhopadhyay

Publikováno v: IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:2148-2157

In this article, we present an effective methodology for co-design, co-analysis and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5D IC designs. In our methodology, we first generate a commercial-grade heteroge

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::13bb8bf8c18fe1b8fa5cfa866a7e9b99
https://doi.org/10.1109/tcpmt.2021.3113664

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Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC

Autor: Satwik Patnaik, Mohammed Nabeel, Venkata Chaitanya Krishna Chekuri, Heechun Park, Sung Kyu Lim, Alabi Bojesomo, Johann Knechtel, Majid Ahadi Dolatsara, Jinwoo Kim, Ozgur Sinanoglu, Madhavan Swaminathan, Saibal Mukhopadhyay

Publikováno v: IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:2047-2060

Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f8ab0111bf2e5210a0f8ba4928236c2a
https://doi.org/10.1109/tcpmt.2020.3033136

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An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage

Autor: Arvind Singh, Venkata Chaitanya Krishna Chekuri, Saibal Mukhopadhyay, Anto Kavungal Davis, Monodeep Kar, Madhavan Swaminathan, Mohamed Lamine Faycal Bellaredj

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 67:3083-3087

Integration of high frequency buck regulators with digital logic in the same die is becoming a standard for next generation processor power delivery. The input voltage of these regulators exceed well beyond the maximum voltage rating of the digital t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c4f69536454df2f938cce567fc0c650a
https://doi.org/10.1109/tcsii.2020.2981129

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Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Autor: Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Kallol Roy, Sung Kyu Lim, Hakki Mert Torun, Hyoukjun Kwon, Nihar Dasari, Madhavan Swaminathan, Tushar Krishna, Eric Qin, Heechun Park, Gauthaman Murali, Saibal Mukhopadhyay, Jinwoo Kim, Minah Lee, Arvind Singh

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2424-2437

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expand

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15cd22d60bab864d35cd250d17d0517e
https://doi.org/10.1109/tvlsi.2020.3015494

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A Digital Low-Dropout Regulator With Autotuned PID Compensator and Dynamic Gain Control for Improved Transient Performance Under Process Variations and Aging

Autor: Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay, Venkata Chaitanya Krishna Chekuri, Monodeep Kar

Publikováno v: IEEE Transactions on Power Electronics. 35:3242-3253

This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process and passive variations, aging, and load changes. The measured results from

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ddf158a02526553ba3759bca4eb90501
https://doi.org/10.1109/tpel.2019.2930490

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Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

Autor: Monodeep Kar, Anand Rajan, Sanu Mathew, Venkata Chaitanya Krishna Chekuri, Vivek De, Arvind Singh, Saibal Mukhopadhyay

Publikováno v: IEEE Journal of Solid-State Circuits. 55:478-493

This article demonstrates enhanced power (P) and electromagnetic (EM) side-channel analysis (SCA) attack resistance of standard (unprotected) 128-bit advanced encryption standard (AES) engines with parallel (P-AES, 128-bit) and serial (S-AES, 8-bit)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d7ac550d8390a68c5dec2deab32d0559
https://doi.org/10.1109/jssc.2019.2945944

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Processing-In-Memory-Based On-Chip Learning With Spike-Time-Dependent Plasticity in 65-nm CMOS

Autor: Dae Hyun Kim, Nael Mizanur Rahman, Xueyuan She, Venkata Chaitanya Krishna Chekuri, Saibal Mukhopadhyay

Publikováno v: IEEE Solid-State Circuits Letters. 3:278-281

A processing-in-memory (PIM)-based accelerator is presented in 65-nm CMOS for on-chip learning in spiking neural network using timing-based stochastic spike-timing-dependent plasticity (STDP). The design uses mixed-signal processing in the 8T-SRAM ar

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c206884710090af931e2bd8d562398a6
https://doi.org/10.1109/lssc.2020.3013448

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