Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Veepsa Bhatia"'
Publikováno v:
International Journal of Technology, Vol 7, Iss 1, Pp 61-70 (2016)
In this paper a new current comparator architecture is presented, which utilizes the concept of nonlinear feedback to speed up the operation. The analytical formulation for quantifying the effect of the feedback is put forward. The functionality
Externí odkaz:
https://doaj.org/article/2c8535bcdd98455da72c5c0f0a676015
Autor:
Veepsa Bhatia, Neeta Pandey
Publikováno v:
Journal of Electrical and Computer Engineering, Vol 2017 (2017)
A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. T
Externí odkaz:
https://doaj.org/article/607c49e141244d808ca370b16289f26b
Publikováno v:
Green Computing in Network Security ISBN: 9781003097198
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60f3226a60eaa0f933b32cf0d9bc0f95
https://doi.org/10.1201/9781003097198-5
https://doi.org/10.1201/9781003097198-5
Autor:
Veepsa Bhatia, Ashu Kawatra
Publikováno v:
2018 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN).
A low Power wide current range current mode comparator is presented in this paper. The current comparator proposed is based on the concept of Threshold Inverter Quantization(TIQ)[8] which accepts one current input. The circuit's output stage gives a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a1384cec0b51be4b7de631ef86cce1f
https://doi.org/10.1109/icacccn.2018.8748345
https://doi.org/10.1109/icacccn.2018.8748345
Autor:
Veepsa Bhatia, Bhilasha Rustogi
Publikováno v:
2018 International Conference on Computing, Power and Communication Technologies (GUCON).
An algorithmic architecture using current mode design techniques offers the designer a small size ADC that is fully compatible with most digital VLSI processes. A new algorithmic current mode ADC is presented in this paper which operates at 1V power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55077d7bb565a909fe605948e5fa74a7
https://doi.org/10.1109/gucon.2018.8674966
https://doi.org/10.1109/gucon.2018.8674966
Publikováno v:
MWSCAS
This paper presents a current comparator based on Source Coupled Logic (SCL) style and its variant called Positive Feedback Source Coupled Logic (PFSCL). It uses three stages namely current to voltage converter, SCL inverter and a PFSCL inverter. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75ae3612c08d4469f86ea0e35b1ecbca
https://doi.org/10.1109/mwscas.2018.8624040
https://doi.org/10.1109/mwscas.2018.8624040
Publikováno v:
2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).
Analog to digital converters (ADC) consists of various components namely, resistor ladder, comparator array, thermometer-to-binary encoder, etc. An error free and highspeed comparator is an important component in ADCs with high resolution and good sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29d9b5ada4eba37607c86eaf16ffa5df
https://doi.org/10.1109/rteict42901.2018.9012379
https://doi.org/10.1109/rteict42901.2018.9012379
Publikováno v:
Journal of The Institution of Engineers (India): Series B. 97:147-154
This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::694525f3088461ec908436395268e934
https://doi.org/10.1007/s40031-015-0189-1
https://doi.org/10.1007/s40031-015-0189-1
Publikováno v:
2017 2nd International Conference on Telecommunication and Networks (TEL-NET).
This paper presents a novel Winner-Take-All (WTA) based current comparator circuit. The proposed comparator employs gain-boosted regulated-cascode CMOS stages at the input node, which offers a very high precision for most of the current mode sensing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f1500f608b9b8c89598a43d37d06c0e
https://doi.org/10.1109/tel-net.2017.8343531
https://doi.org/10.1109/tel-net.2017.8343531
Autor:
Neeta Pandey, Veepsa Bhatia
Publikováno v:
Communications in Computer and Information Science ISBN: 9789811054266
A novel ultra low power current comparator has been proposed in this paper. The current comparator utilizes Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technique to reduce the power dissipation, by reducing the supply voltage. The circuit is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::172898efbb8f6dff66dc8748d86ad95f
https://doi.org/10.1007/978-981-10-5427-3_45
https://doi.org/10.1007/978-981-10-5427-3_45