Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Vasantha Moodabettu Harishchandra"'
Autor:
Sithara Raveendran, Nithin Kumar Yernad Balachandra, Pranose J. Edavoor, Vasantha Moodabettu Harishchandra
Publikováno v:
IET Image Processing. 14:4110-4121
This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image wi
Autor:
Nithin Kumar Y. B, Edoardo Bonizzoni, Vasantha Moodabettu Harishchandra, Siddharth Rajkumar Kala, Sushma Chandaka
Publikováno v:
IET Circuits, Devices & Systems. 14:340-346
The need for the high-speed analogue-to-digital converters demands the use of regenerative comparators. The strong positive feedback present in the regenerative comparators helps the comparator to work efficiently at the high-speed operations. This w
Publikováno v:
IET Circuits, Devices & Systems. 13:988-997
The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order G m-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the idea
Publikováno v:
Telecommunication Systems. 68:621-630
Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the w
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra
Publikováno v:
Sustainable Computing: Informatics and Systems. 16:1-10
Network on Chip (NoC) has been proposed as an efficient solution to communication problems in on-chip processors. The probability of failure increases in these systems because the complexity involved in continuous device scaling and the number of com
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra
Publikováno v:
Microelectronics Journal. 70:16-26
This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a core graph unit, which is responsible for mapping and scheduling the core graph on the NoC architecture. Fault tolerance unit collects all the fault informati
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra
Publikováno v:
Wireless Personal Communications. 100:213-225
Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient
Akademický článek
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Akademický článek
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Publikováno v:
2012 4th Asia Symposium on Quality Electronic Design (ASQED).
This paper presents a low voltage, low power continuous-time (G m -C) 4th order low pass Butterworth filter with a 3-dB bandwidth of 1MHz and capable of operating at supply voltage as low as 0.5V in 0.18 µm. The filter uses bulk-driven technique for