Výsledky vyhledávání - "Vance H. Adams"

Through-Silicon-Via stress 3D modeling and design

Autor: Thuy B. Dao, Vance H. Adams

Publikováno v: 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the suc

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::51e3a44b76a0fb817ded9683e5be97df
https://doi.org/10.1109/icicdt.2010.5510281

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Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Autor: Mike Petras, Vance H. Adams, Brian D. Griesbach, Tom Kropewnicki, Dina H. Triyoso, Doug Booker, Thuy B. Dao, Rode R. Mora

Publikováno v: Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f62768624a111ddbc85d0a4eb0c0f699
https://doi.org/10.1109/vdat.2010.5496677

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An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

Autor: L. Prabhu, Bruce E. White, Paul A. Grudowski, R. Garcia, Aaron Thean, V. Dhandapani, H. Desjardins, D. Weeks, Vance H. Adams, D. Tekleab, Stefan Zollner, M. Foisy, David Theodore, Matthias Bauer, Darren V. Goedeke, Konstantin V. Loiko, Gregory S. Spencer, Shawn G. Thomas

Publikováno v: 2007 IEEE International SOI Conference.

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increas

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4e88ddc23a0c29605a2a42834482eb8f
https://doi.org/10.1109/soi.2007.4357831

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Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

Autor: Venkat R. Kolagunta, Xiang-Zheng Bo, M. Foisy, Surya Veeraraghavan, Lixin Ge, Vance H. Adams, D. Tekleab, Konstantin V. Loiko

Publikováno v: 2007 IEEE International SOI Conference.

We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::629568968978b9f2717f1adba6e6223d
https://doi.org/10.1109/soi.2007.4357835

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1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Autor: M. Jahanbani, Jon D. Cheek, N. Cave, S.j. Lian, Konstantin V. Loiko, Mehul D. Shroff, Chi-Hsi Wu, Stanley M. Filipiak, Xiang-Zheng Bo, H.C. Tuan, M. Azrak, Paul A. Grudowski, Wen-Jya Liang, Vance H. Adams, Sinan Goktepeli, Venkat R. Kolagunta, M. Foisy, John J. Hackenberg

Publikováno v: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit desig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::33649abd039e0c65218d78c61cea5101
https://doi.org/10.1109/vlsit.2006.1705217

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Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

Autor: S. Filipiak, M. Foisy, John J. Hackenberg, Hsiao-chin Tuan, Xiang-Zheng Bo, Venkat R. Kolagunta, Konstantin V. Loiko, Li-te Lin, Jon Cheek, Paul A. Grudowski, D. Tekleab, Chi-hsi Wu, Vance H. Adams, K.h. Fung

Publikováno v: 2006 IEEE international SOI Conferencee Proceedings.

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6e04e380e001b0d73f4de7f4d79ff883
https://doi.org/10.1109/soi.2006.284411

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Multi-Layer Model for Stressor Film Deposition

Autor: Stanley M. Filipiak, Paul A. Grudowski, Brian J. Goolsby, Konstantin V. Loiko, M. Foisy, Venkat R. Kolagunta, D. Tekleab, Brian A. Winstead, Xiang-Zheng Bo, Sinan Goktepeli, Vance H. Adams

Publikováno v: 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0e856f411e2a7a44742f291e7e69bf5a
https://doi.org/10.1109/sispad.2006.282853

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Stress Sensitivity of PMOSFET Under High Mechanical Stress

Autor: D. Tekleab, Vance H. Adams, Paul A. Grudowski, S. Parsons, M. Foisy, Brian A. Winstead, Konstantin V. Loiko

Publikováno v: 2006 International Conference on Simulation of Semiconductor Processes and Devices.

Using PMOSFETs with a range of built-in process induced stress and four-point bending characterization, we present evidence that the stress response of PMOSFETs increases with channel stress. A novel method incorporating the characterization data wit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15a20585b850fddb2b09f5450ec9ebab
https://doi.org/10.1109/sispad.2006.282852

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65nm SOI CMOS Technology for High Performance Microprocessor Application

Autor: S.j. Lian, H.C. Tuan, Omar Zia, N. Cave, Vance H. Adams, Jon D. Cheek, C.t. Yang, Paul A. Grudowski, Chi-Feng Wu, Byoung W. Min, Samuel Fung, D.h. Lee, N. Grove, H.t. Huang, K.h. Chen, W.j. Liang, Venkat R. Kolagunta

Publikováno v: 2006 International Symposium on VLSI Technology, Systems, and Applications.

This paper presents a state-of-the-art 65nm SOI CMOS transistor technology target for high performance microprocessor application. N/PFET shows short channel control meeting manufacturing margin at 32/35nm respectively. By using dual contact etch sto

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::196da53871f74eabf1cec08b2313e6e7
https://doi.org/10.1109/vtsa.2006.251065

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Exploration of the Scaling Limits of 3D Integration

Autor: Stefan Zollner, Michael Canonico, Vance H. Adams, Scott K. Pozder, Robert E. Jones, Ronald J. Gutmann, Hui-Feng Li, Sang Hwui Lee, Jian-Qiang Lu

Publikováno v: MRS Proceedings. 970

Three dimensional (3D) wafer bonding is an emerging technology that may be used to increase transistor densities by stacking devices over devices. The alignment of the wafers and the devices on them is a function of the mechanical capability of the w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f98786e9cec1f774d1d46e1986daa25d
https://doi.org/10.1557/proc-0970-y02-01

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