Zobrazeno 1 - 10
of 32
pro vyhledávání: '"Vamsi Boppana"'
Autor:
Juanjo Noguera, Sridhar Subramanian, Ralph D. Wittig, Shankar Lakka, Gaurav Singh, Vamsi Boppana, Sagheer Ahmad, Fu-Hing Ho, Tomai Knopp
Publikováno v:
Hot Chips Symposium
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bd6b2338ad9d3365067c72a4ed73be3
https://doi.org/10.1109/hotchips.2019.8875639
https://doi.org/10.1109/hotchips.2019.8875639
Autor:
Vamsi Boppana, Vinod K. Kathail, Ilya K. Ganusov, Vidya Rajagopalan, Ralph D. Wittig, Sagheer Ahmad
Publikováno v:
IEEE Micro. 36:48-62
This article presents the Zynq UltraScale+ MPSoC (multiprocessor system on chip), which builds on the Zynq-7000 family. Compared to the first-generation Zynq, MPSoC increases performance and power efficiency while significantly improving the integrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c854debaf312e2fad9e92ecf1104588
https://doi.org/10.1109/mm.2016.18
https://doi.org/10.1109/mm.2016.18
Autor:
Vidya Rajagopalan, Sagheer Ahmad, Ralph D. Wittig, Vinod K. Kathail, Ilya K. Ganusov, Vamsi Boppana
Publikováno v:
Hot Chips Symposium
This article consists of a collection of slides from the authors' conference presentation. Zynq UltraScale+ MPSoC: 2nd Generation SoC from Xilinx - Applications processing, Real-time, Graphics, Video, Serial connectivity - Power management, Safety, S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3545207fa4d450d049831a3b262c655b
https://doi.org/10.1109/hotchips.2015.7477457
https://doi.org/10.1109/hotchips.2015.7477457
Publikováno v:
2011 IEEE Hot Chips 23 Symposium (HCS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca6f59ab7521b2830d703e4ee8a4efcc
https://doi.org/10.1109/hotchips.2011.7477495
https://doi.org/10.1109/hotchips.2011.7477495
Autor:
Vamsi Boppana, Shashank Bhonge
Publikováno v:
ISLPED
Summary form only given. The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party fou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fefb79cde342056f1de62b9db2d8f27f
https://doi.org/10.1145/1393921.1394013
https://doi.org/10.1145/1393921.1394013
Publikováno v:
Nano, Quantum and Molecular Computing ISBN: 1402080670
Any nano-system that designers build must guarantee functional correctness. The sheer scale factor and the added layers of uncertainty in nano-systems demand revolutionary breakthroughs in system design tools and algorithms. Formal verification of na
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d30645f0aaf0eb8de9d14d4de945086
https://doi.org/10.1007/1-4020-8068-9_11
https://doi.org/10.1007/1-4020-8068-9_11
Autor:
Debashis Bhattacharya, Vamsi Boppana
Publikováno v:
Closing the Gap Between ASIC & Custom ISBN: 1402071132
The set of flex-cells, either alone or in combination with standard-cells, provides an optimally tuned set of building blocks for the target IC design, where optimality is measured against accepted and definable (i.e. quantifiable) metrics like clock
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88fc8cac0a56e819aa9fbcace9b3f409
https://doi.org/10.1007/0-306-47823-4_10
https://doi.org/10.1007/0-306-47823-4_10
Publikováno v:
DAC
With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows \citeITRS02. The effect of layout parasitics is considerable even at the intra-cell level in standard
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26b131713d34b932058be3d193e03ff9
https://doi.org/10.1145/996566.996626
https://doi.org/10.1145/996566.996626
Publikováno v:
Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).
This paper presents an efficient BIST solution for VLSI circuit testing based on GF(2/sup p/) CA (cellular automata on an extended Galois field). The novel architecture of GF(2/sup p/) CA permits the BIST structure to be highly customized to the circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97731910ab3d454a864e3c3feece743e
https://doi.org/10.1109/aspdac.2001.913326
https://doi.org/10.1109/aspdac.2001.913326
Autor:
Kolin Paul, G.P. Biswas, Suchita Mukherjee, P. Pal Chaudhuri, C. Yang, Biplab K. Sikdar, Vamsi Boppana
Publikováno v:
VLSI Design
This paper sets a new direction for test solution of VLSI circuits. The solution is based on the theory of extension field-that is, extension of finite field commonly referred to as Galois field (GF). The GF(2) with the set {0,1} traditionally employ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55a96325745841f5fc97966dcf9d204e
https://doi.org/10.1109/icvd.2000.812666
https://doi.org/10.1109/icvd.2000.812666