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pro vyhledávání: '"Value change dump"'
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Autor:
Daeun Heo, Daejin Park
Publikováno v:
ICEIC
This paper proposes a real-time asynchronous web application on NodeJS, which parses the value change dump (VCD) files from servers to JSON (JavaScript Object Notation) files and efficiently communicates waveform simulations to clients, thereby avoid
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5f0fc635560e85c48804a6e5d169fe0
https://doi.org/10.1109/iceic51217.2021.9369755
https://doi.org/10.1109/iceic51217.2021.9369755
Autor:
Roberto Ugioli, Paolo Bernardi, S. Quer, S. Littardi, Giorgio Pollaccia, D. Appello, V. Tancorre, A. Calabrese
Publikováno v:
DDECS
With the explosion of off-the-shelf SoCs in terms of size and the advent of novel techniques related to failure modes, commercial ATPG and fault simulation engines can often be insufficient to measure the coverage of very specific metrics. In these c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::384500985511f3510f271aa95d5f8409
http://hdl.handle.net/11583/2909176
http://hdl.handle.net/11583/2909176
Autor:
Xu Shou-quan
Publikováno v:
DSA
According to the shortcomings of low real-time simulation test and insufficient physical test in the process of Field-Programmable Gate Array (FPGA) software test.. FPGA physical automation verification technology based on Value Change Dump (VCD) wav
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7230c2875437618b416d1716af461a4e
https://doi.org/10.1109/dsa51864.2020.00050
https://doi.org/10.1109/dsa51864.2020.00050
Autor:
Sumit Soin, Gurvinder Singh
Publikováno v:
2018 International Conference on Computing, Power and Communication Technologies (GUCON).
Post-Silicon design validation of digital ASICs on Automated-Test-Equipment (ATE) require test vectors for chip functional verification. These test vectors are generated by running post-layout design simulations. Integrated Circuit (IC) Design tools
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ecd6a731e57222536fdd0d7d5682bb2
https://doi.org/10.1109/gucon.2018.8674958
https://doi.org/10.1109/gucon.2018.8674958
Publikováno v:
2018 International Conference on Computing, Mathematics and Engineering Technologies (iCoMET).
Assertion Based Verification (ABV) has been shown to be a very effective functional verification approach for digital designs. ABV is usually employed by the verification engineers by embedding assertions in the hardware description language (HDL) co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b54bbb19a80a8eb94fd5f12f732f39f2
https://doi.org/10.1109/icomet.2018.8346391
https://doi.org/10.1109/icomet.2018.8346391
Autor:
Erik Jan Marinissen, Alkis A. Hatzopoulos, Christos Papameletis, Leonidas Katselas, Hailong Jiao, Angelos Athanasiadis
Publikováno v:
Proceedings of IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation 2017, 1-8
STARTPAGE=1;ENDPAGE=8;TITLE=Proceedings of IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation 2017
PATMOS
STARTPAGE=1;ENDPAGE=8;TITLE=Proceedings of IEEE International Symposium on Power and Timing Modeling, Optimization, and Simulation 2017
PATMOS
In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. To create test conditions which are as similar as possible to functional modes, today’s ATPG tools have knobs to constrain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7168fd168ded95f2a9e48d4d3e6f2338
https://research.tue.nl/nl/publications/14d9fbae-ea50-45c3-88e6-6a57c620b246
https://research.tue.nl/nl/publications/14d9fbae-ea50-45c3-88e6-6a57c620b246
Autor:
Andrei Tchernykh, Godofredo R. Garay, Sergey N. Garichev, Moisés Torres-Martinez, Alexander Yu. Drozdov, Sergio Nesmachnow
Publikováno v:
Journal of Computational Science. 36:100652
Communication between information processing systems becomes a challenge, especially in the “big data” era. It is a mandatory subject in the topic “Architecture and organization” of the computer science curriculum. However, in our experience,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da0775af97564f7721d5a8f66ed3ac9c
https://doi.org/10.1016/j.jocs.2017.04.004
https://doi.org/10.1016/j.jocs.2017.04.004
Autor:
Witold A. Pleskacz, Krzysztof Marcinek
Publikováno v:
Microprocessors and Microsystems. 37:693-700
Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock frequency reveals the necessity for dynamic and smart utilizati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1f03cbc84a3ea782f077a2523ed4a0f
https://doi.org/10.1016/j.micpro.2012.06.004
https://doi.org/10.1016/j.micpro.2012.06.004
Publikováno v:
ISCAS
System Python (SysPy) is a public domain design tool using Python to facilitate all prototyping phases of processor-centric SoCs for FPGAs. In previous work we used Python as a high-level description mechanism to design hardware modules and connect t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4a067039b5fe39e7c5b8a9aac2a4eb6
https://doi.org/10.1109/iscas.2016.7527465
https://doi.org/10.1109/iscas.2016.7527465