Zobrazeno 1 - 10 of 14 pro vyhledávání: '"V.SH. MELIKYAN"'
1
Power and Ground Metal Insertion into Integrated Circuit Design Combined with Timing Aware Dummy Metal Fill Insertion
Autor: Suren Abazyan, V.Sh. Melikyan
Publikováno v: Proceedings of Universities. Electronics. 26:226-233
As dummy metal fill insertion is mandatory step for integrated circuits’ (IC) current manufacturing processes, many works are targeting better fill insertion with small coupling capacitance. However, with scaling technology trends, smaller IR drop
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bb08e0157a561f04aa4ef9baef6ba0f9
https://doi.org/10.24151/1561-5405-2021-26-3-4-226-233
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2
High Accuracy Two-Step Flash ADC with Changeable Comparison Range Using Latch Based Comparator
Autor: V.Sh. Melikyan, Vazgen Gevorgyan
Publikováno v: Proceedings of Universities. Electronics. 26:273-281
Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f15a6776085638d34451423974df15b9
https://doi.org/10.24151/1561-5405-2021-26-3-4-273-281
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3
THE AGING INFLUENCE MINIMIZATION METHOD FOR OPERATIONAL AMPLIFIERS WITH THIN OXIDE TRANSISTORS
Autor: V.SH. MELIKYAN, S.A. GHUKASYAN, S.S. HARUTYUNYAN, H.T KOSTANYAN, G.A. VOSKANYAN
Publikováno v: Proceedings.
Nowadays CMOS technology feature size is being scaled aggressively. Supply voltage is not proportionally scaled, gate dielectric thickness is reduced and as a result, the devices are subjected to stronger electric fields, thereby causing stress on tr
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::87f230cf65673a403d38014dfc7c7aca
https://doi.org/10.53297/0002306x-2022.v75.4-527
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6
Power Efficient, Low Noise 2-5 GHz Phase Locked Loop
Autor: V.Sh. Melikyan, A.A. Durgaryan, H.P. Petrosyan, A.G. Stepanyan
Publikováno v: Electronics and Communications. 16:66-72
A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the P
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::34e2cb37c3e084c86bc1b0b2ec7b3db2
https://doi.org/10.20535/2312-1807.2011.16.4.244797
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7
Method of Parametrical Optimization of Multi-Core Processors
Autor: V.Sh. Melikyan, A. M. Poghosyan, A.A. Durgaryan, H.P. Petrosyan, M.M. Simonyan
Publikováno v: Electronics and Communications. 16:126-130
A post-layout design power optimization algorithm is suggested. Both, gate sizing andmulti threshold optimization methods are implemented. The main advantages are the improved performance characteristics and intactness of the initial design placement
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::538c5d13b214afad10d4de9cab1d2b52
https://doi.org/10.20535/2312-1807.2011.16.3.266228
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8
Conference
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9
Conference
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10
Akademický článek
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