Zobrazeno 1 - 10
of 32
pro vyhledávání: '"V. von Kaenel"'
Autor:
G. Yiu, M. Pearce, Daniel C. Murray, Robert Rogenmoser, Dongwook Suh, Zongjian Chen, S. Nishimoto, D. Rodriguez, V. von Kaenel, E. Supnet, M. Oyker
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1857-1865
The load/store pipe for a low-power 1-GHz embedded processor is described. For area savings and logic complexity reduction, the load/store pipe is clocked at twice the frequency of the processor core. It can sustain two load or store operations per c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa174e9c105904d3d6f041efcc9ed15d
https://doi.org/10.1109/jssc.2003.818296
https://doi.org/10.1109/jssc.2003.818296
Autor:
Ingino Joseph M, V. von Kaenel
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1693-1698
A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c83a460699af945c5e523b906b621197
https://doi.org/10.1109/4.962289
https://doi.org/10.1109/4.962289
Autor:
V. von Kaenel
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1634-1639
This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f92db9130131218b7d6315f22229a251
https://doi.org/10.1109/4.726549
https://doi.org/10.1109/4.726549
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:999-1005
A micropower crystal oscillator module for watch applications is presented. The integrated circuit is encapsulated with a 2.1-MHz crystal in a miniature vacuum package to reduce parasitic effects. The circuit comprises frequency tuning with a resolut
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d4db070b1ec9d6688f8b7cc094ba528
https://doi.org/10.1109/4.597290
https://doi.org/10.1109/4.597290
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1715-1722
This paper describes a low-power microprocessor clock generator based upon a phase-locked loop (PLL). This PLL is fully integrated onto a 2.2-million transistors microprocessor in a 0.35-/spl mu/m triple-metal CMOS process without the need for extern
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3be2a74ed3f3b98f02a6748b5f08e09
https://doi.org/10.1109/jssc.1996.542316
https://doi.org/10.1109/jssc.1996.542316
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:1136-1140
Two techniques for voltage reduction are presented, both of which can significantly reduce the power consumption of digital CMOS circuits. The fixed reduction of voltage is applicable to small systems with a low initial consumption, however, the opti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c6d592ec1bdee634c1446a7bd1aae6c
https://doi.org/10.1109/4.62134
https://doi.org/10.1109/4.62134
Publikováno v:
CICC
The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and powe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e8a82d7102400ee7fe6fdb175e12517
https://doi.org/10.1109/cicc.2007.4405834
https://doi.org/10.1109/cicc.2007.4405834
Autor:
Toshinari Takayanagi, V. von Kaenel
Publikováno v:
CICC
Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0999e385591ece523022bd9bfc75bfc
https://doi.org/10.1109/cicc.2007.4405730
https://doi.org/10.1109/cicc.2007.4405730
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
This paper reports on the design of a phase-locked-loop (PLL) for on-chip clock generation for a high-performance microprocessor (/spl mu/P). The power consumption of the /spl mu/P has been reduced by scaling down the supply voltage. The whole system
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b2e2cb38993cdf9300f77fa97726f99
https://doi.org/10.1109/isscc.1996.488540
https://doi.org/10.1109/isscc.1996.488540
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
Low-power single-cell battery-operated fully-featured radio receivers, with a minimum of external components are hard to find. Classical low-voltage heterodyne receivers consisting of bipolar transistor arrays require 50 to 60 external components to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::403f816abaa76fe7074ec0a52f8dc34f
https://doi.org/10.1109/isscc.1996.488712
https://doi.org/10.1109/isscc.1996.488712