Zobrazeno 1 - 10
of 16
pro vyhledávání: '"V. Staroselsky"'
Autor:
K. Kim, A. V. Staroselsky
Publikováno v:
Rock Mechanics and Rock Engineering. 30:145-159
We explain analytically the effects of surfactants on the enhancement of drilling rates in rock. We propose that the weakening effect is not simply due to the chemical action of the surfactant, as suggested by Rebinder in the 1930's but to a combinat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c130168560c0019037e229744b9fac6f
https://doi.org/10.1007/bf01047390
https://doi.org/10.1007/bf01047390
Autor:
V. Staroselsky, T. Schlichter, E. Bushehri, W. Daumann, M. Agethen, Franz-Josef Tegude, V. Bratov, W. Brockerhoff, A. Brennemann, R.M. Bertenburg
Publikováno v:
ICECS
This paper describes the InP-based HFET technology for the implementation of high bitrate logic gates. A novel logic gate configuration is presented based on depletion mode HFETs (DHFET) using a nonlinear negative feedback (NNFB) for optimized high s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1686aff48f631070f807e38a88cccccc
https://doi.org/10.1109/icecs.1998.814016
https://doi.org/10.1109/icecs.1998.814016
Autor:
V. Staroselsky, A. Brennemann, V. Bratov, T. Schlichter, M. Agethen, R.M. Bertenburg, W. Brockhoff, Franz-Josef Tegude, E. Bushehri
This paper presents the performance of an 11-stage ring oscillator for high speed digital circuits using a gate configuration with nonlinear negative feedback (NNFB). An additional transistor is introduced into the switching path of buffered FET logi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ff7b981e7729a6e3df024dd8a9e65ae7
https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&origin=inward&scp=0033723553
https://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&origin=inward&scp=0033723553
A T&H circuit with a sampling rate of 6 Gsample/s has been experimentally demonstrated in AlGaAs/GaAs/AlGaAs HEMT technology. The circuit utilises a dual bridge topology suitable for interleaved ADC circuits, doubling the effective sampling rate with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::92e768981fa3728352a81387c5ba4de4
https://publica.fraunhofer.de/handle/publica/192362
https://publica.fraunhofer.de/handle/publica/192362
Publikováno v:
IEE Colloquium on Advanced Developments in Microelectronic Engineering.
Over the past few years there has been a steady progress in the development of digital GaAs technologies providing VLSI complexity to the high speed system designers. The improvements in the fabrication process have resulted in the emergence of over
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c489e6ea9a1328eed95dda7b69c29219
https://doi.org/10.1049/ic:19961243
https://doi.org/10.1049/ic:19961243
Publikováno v:
Electronics Letters. 31:1828-1829
Design and evaluation of a novel high speed low power static RAM cell in AlGaAs/GaAs quantum well technology is presented. A current sense amplifier to accompany this cell is also proposed. Simulation results show an access time of 700 ps with standb
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9395f58829bbea509cdb27dda019c48d
https://doi.org/10.1049/el:19951278
https://doi.org/10.1049/el:19951278
Autor:
V. Bratov, V. Staroselsky, M. Rieger-Motzer, A. Huelsmann, A. Thiede, B. Raynor, E. Bushehri, T. Schlichter
Publikováno v:
IEE Proceedings - Circuits, Devices and Systems. 144:243
Evaluation of a high-performance logic gate configuration, utilising enhancement mode field effect transistors, is presented in AlGaAs/GaAs/AlGaAs quantum well HEMT technology. The performance of the gate in terms of speed, based on frequency divider
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1a85e8c25da17156aab4ab2f3be9cab
https://doi.org/10.1049/ip-cds:19971145
https://doi.org/10.1049/ip-cds:19971145
Publikováno v:
IEE Proceedings - Circuits, Devices and Systems. 142:394
Ultra-high-speed logic gates are proposed using heterostructure field-effect transistors. A simple noise margin optimisation method is applied to improve the performance in terms of noise margin and delay. A 16-bit binary carry look-ahead adder is th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8fb7ab303405fb1683d7658f96ace447
https://doi.org/10.1049/ip-cds:19952257
https://doi.org/10.1049/ip-cds:19952257
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.