Zobrazeno 1 - 10
of 43
pro vyhledávání: '"V. N. Sekhar"'
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Autor:
S. Bhattacharya, T. G. Lim, D. Ho, K. J. Chui, X. W. Zhang, M. D. Rotaru, B. G. Sajay, T. C. Chai, S. C. Chong, H. Y. Li, S. Lim, X. Y. Wang, M. C. Jong, V. N. Sekhar, R. Dutta, Vempati S. Rao
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:304-313
In this study, fan-out panel-level packaging (FO-PLP) technology using a redistribution layer (RDL) first approach is demonstrated using a large glass panel as a carrier (550 mm $\times650$ mm size). Finite-element analysis (FEA) is conducted to inve
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 7, Pp 1209-1216 (2019)
Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si i
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
In this study, fan-out panel level packaging (FO-PLP) technology using redistribution layer (RDL) first approach is demonstrated using Gen-3 glass substrate (550mm × 650mm size). Investigation on panel level warpage during process is carried out thr
Autor:
Sharon Lim Pei Siang, Surya Bhattacharya, Wang Xiang Yu, Jayabalan Jayasanker, V. N. Sekhar, Vivek Chidambaram
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
Achieved system scaling by implementing key system functions into active interposer. Demonstrated partitioning of System on Chip (SoC) to smaller dies to achieve lower cost and higher yield. Heterogeneous integration involving 130 nm active silicon i
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
For the study of active device effect by fan-out wafer level packaging process, fan-out assembly processes were simulated by using actual CMOS device wafers as carrier to study the device performance effect. The I d V d and I d V g of 65nm technology
Autor:
V. N. Sekhar, Hiroshi Matsui, Takaya Yoshiteru, Horiguchi Yukio, Kazunori Yamamoto, Koichi Jono, Vempati Srinivasa Rao, Tetsushi Fujinaga
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
Present study focuses on lithography evaluation of dielectric and resist materials for panel level fan out fabrication. All experiments have been conducted on Gen 3 (550x650mm) size glass panels. Slit coating and Laser Direct Imaging (LDI) methods ha
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
Present study focuses on high aspect ratio Thru Mold Via (TMV) fabrication using nanosecond laser drill tool. Epoxy mold compound (EMC) with 25um filler size is used to demonstrate 50um diameter TMV. Smaller via size with increase in high I/O count a
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
Non-Conductive Film (NCF) is an attractive option for tacking the chip on the wafer before sending the tacked sample to gang bonder to form the solder interconnects. Chip on Wafer (CoW) bonding is a preferred choice over wafer to wafer bonding as it