Zobrazeno 1 - 5
of 5
pro vyhledávání: '"V. Migairou"'
Publikováno v:
Journal of Embedded Computing. 3:221-229
The increase of within-die variations and the design margin growth are creating a need for statistical design methodologies. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts that occur during p
Publikováno v:
6èmes Journées d'Etudes Faible-Tension Faible Consommation
FTFC: Faible Tension-Faible Consommation
FTFC: Faible Tension-Faible Consommation, May 2007, Paris, France. pp.19-25
Lecture Notes in Computer Science ISBN: 9783540744412
PATMOS
17th International Conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
FTFC: Faible Tension-Faible Consommation
FTFC: Faible Tension-Faible Consommation, May 2007, Paris, France. pp.19-25
Lecture Notes in Computer Science ISBN: 9783540744412
PATMOS
17th International Conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2007, Gothenburg, Sweden. pp.138-147, ⟨10.1007/978-3-540-74442-9_14⟩
International audience; The increase of within-die variations and design margins is creating a need for statistical design methods. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts occurring du
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::de31405db7e7c018066aa358586a964c
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00178454
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00178454
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540390947
PATMOS
16th International Workshop on Power and Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
PATMOS
16th International Workshop on Power and Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation
PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2006, Montpellier, France. pp.468-476, ⟨10.1007/11847083_45⟩
International audience; With the scaling of technology, the variability of timing performances of digital circuits is increasing. In this paper, we propose a first order analytical modeling of the standard deviations of basic CMOS cell timings. The p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b678f628489c16f0805921e0e5452518
https://doi.org/10.1007/11847083_45
https://doi.org/10.1007/11847083_45
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