ExaNoDe: Combined Integration of Chiplets on Active Interposer with Bare Dice in a Multi-Chip-Module for Heterogeneous and Scalable High Performance Compute Nodes

Autor: J. Durupt, Dominique Drouin, Yann Beilliard, P.-Y. Martinez, Severine Cheramy, David Danovitch, A. Philippe, Arnaud Garnier, P. Coudrain, C. Fuguet Tortolero, Pascal Vivet, Denis Dutoit, Didier Lattard, Jean Charbonnier, Maxime Godard, V. Mengue, Eric Guthmuller

Publikováno v: 2020 IEEE Symposium on VLSI Technology
2020 IEEE Symposium on VLSI Technology, Jun 2020, Honolulu, IEEE, pp.1-2, 2020, ⟨10.1109/VLSITechnology18217.2020.9265100⟩

In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for den

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https://hal.archives-ouvertes.fr/hal-03178715