Zobrazeno 1 - 10
of 233
pro vyhledávání: '"V. Kripesh"'
Publikováno v:
Health and Technology. 7:153-159
In rural areas, people die at their early ages because of lack of proper facilities and infrastructure for monitoring patient’s health at the right time. Therefore, the design and development of a Remote Patient Monitoring System (RPMS) has a lot o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21385d5c9fb079b5e08089ebe04d1b9d
https://doi.org/10.1007/s12553-016-0171-1
https://doi.org/10.1007/s12553-016-0171-1
Autor:
Tan Siow Pin, Damaruganath Pinjala, N. Khan, Toh Kok Chuan, Soon Wee Ho, V. Kripesh, John H. Lau, Li Hong Yu
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 3:221-228
In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3a1785210b05c6745f8b8443b13eb2c
https://doi.org/10.1109/tcpmt.2012.2186297
https://doi.org/10.1109/tcpmt.2012.2186297
Autor:
John H. Lau, Scott Chen, Chih-Ming Huang, Jong Ming Ching, Chien-Feng Chan, Chin-Huang Chang, Chi-Hsin Chiu, Carl Chen, V. Kripesh, Chang-Yueh Chan, Aibin Yu, Nandar Su, Aditya Kumar, Khong Chee Houe, Soon Wee Ho, Hnin Wai Yin, Chun-Chieh Chao
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:1777-1785
The development of ultrafine-pitch microbumps and the thermal compression bonding (TCB) process for advanced 3-D stacking technology are discussed in this paper. Microbumps, consisting of Cu pillars and thin Sn caps with a pitch of 25 μm, are fabric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6a4fdaa842d54ba73d9eeaa82d838e6
https://doi.org/10.1109/tcpmt.2012.2203130
https://doi.org/10.1109/tcpmt.2012.2203130
Autor:
Rao Tummala, Xiaowu Zhang, Dim-Lee Kwong, Ranjan Rajoo, N. Khan, V. Kripesh, Aditya Kumar, Vempati Srinivasa Rao, Venky Sundaram, John H. Lau, C. S. Selvanayagam
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:935-943
Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b4258131c721fe50e5c666d8ca2a668
https://doi.org/10.1109/tcpmt.2012.2192731
https://doi.org/10.1109/tcpmt.2012.2192731
Autor:
C. S. Premchandran, Xiaowu Zhang, V. N. Sekhar, V. Kripesh, John H. Lau, Seung Wook Yoon, Lu Shen, Aditya Kumar, Tai Chong Chai
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:3-12
This paper presents the effect of back grinding on the mechanical properties of the active side of the multilayered low-k stacked die. Low-k stacked wafers were thinned to four different thicknesses of 500, 300, 150, and 75 μm by using a commercial
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0abd5ae202bda8182717932287c4695c
https://doi.org/10.1109/tcpmt.2011.2141989
https://doi.org/10.1109/tcpmt.2011.2141989
Autor:
Chi-Hsin Chiu, Wen-Sheng Lee, V. N. Sekhar, V. Kripesh, Ming Ching Jong, Carl Chen, Chih-Ming Huang, Damaruganath Pinjala, John H. Lau, Scott Chen, Soon Wee Ho, Chun-Chieh Chao, Aibin Yu, Chien-Feng Chan, Aditya Kumar, Wai Yin Hnin
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:1336-1344
Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ead0c5b91a58bf78e4eb3cadd69e1104
https://doi.org/10.1109/tcpmt.2011.2155655
https://doi.org/10.1109/tcpmt.2011.2155655
Autor:
Georg Meyer-Berg, Aditya Kumar, Guanbo Huang, Q. X. Zhang, Dim-Lee Kwong, R.R. Tummula, Venky Sundaram, C. Lee, John H. Lau, Xiaowu Zhang, Ming Chinq Jong, Lee Wen Sheng Vincent, V. Kripesh
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:841-851
In this paper, piezoresistive stress sensors have been used to analyze the residual stress in thin device wafers. For the analysis, device wafers having piezoresistive stress sensors were fabricated. The stress sensors were then calibrated to determi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15cc297c418d4364a801d9b0802be2d7
https://doi.org/10.1109/tcpmt.2011.2135353
https://doi.org/10.1109/tcpmt.2011.2135353
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:502-509
Die shift problem that arises during the wafer molding process in embedded micro wafer level package fabrication was systematically analyzed and solution strategies were developed. A methodology to measure die shift was developed and applied to creat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd3f98c76f7bd17bb262be8325fcdfc9
https://doi.org/10.1109/tcpmt.2010.2100431
https://doi.org/10.1109/tcpmt.2010.2100431
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:536-544
Demand for increased functionalities and the trend in product miniaturization have created new challenges for electronic packaging. The move to 3-D packages combines the benefits of small footprint packages and through-silicon-vias technology to over
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc80e5f84dc37e2fb3124843de8c54cb
https://doi.org/10.1109/tcpmt.2010.2100710
https://doi.org/10.1109/tcpmt.2010.2100710
Autor:
C. S. Premachandran, V. Kripesh, Fa Xing Che, John H. Lau, S. C. Chong, Xiaowu Zhang, V. N. Sekhar, T. C. Chai, Leong Ching Wai, Damaruganath Pinjala, V Lee
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:299-309
Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips into one package becomes a popular choice. In this paper, the development of a three-die stack
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da60a63d5e071a3fe1d5a7fc07dd1097
https://doi.org/10.1109/tcpmt.2010.2100292
https://doi.org/10.1109/tcpmt.2010.2100292