Zobrazeno 1 - 7
of 7
pro vyhledávání: '"V. I. Enns"'
Publikováno v:
Russian Microelectronics. 51:579-584
Publikováno v:
Russian Microelectronics. 50:509-515
The problem of analyzing and evaluating the structure of FPGA routing resources at early stages of the design flow presents great interest for researchers. Until now, an approach, consisting in passing the full design flow (logic synthesis, placement
Publikováno v:
Russian Microelectronics. 50:463-470
Publikováno v:
Russian Microelectronics. 50:426-438
Autor:
V. I. Enns, S.V. Gavrilov, Mariya A. Zapletina, V.M. Khvatov, R. Zh. Chochaev, D. A. Zheleznikov
Publikováno v:
Russian Microelectronics. 48:176-186
A layout synthesis design flow for implementing designs on reconfigurable systems-on-chip is developed by the Institute for Design Problems in Microelectronics of Russian Academy of Sciences, in cooperation with JSC “NIIME” for special-purpose ci
Publikováno v:
Russian Microelectronics. 46:494-499
This paper considers the design features of parameterized analog cells based on the matched matrix elements for the SOI technology. A technique for synthesizing such cells is developed. Some examples are presented of the program code for building par
Publikováno v:
Semiconductors. 43:1728-1731
A new principle of arranging temperature measurements in integrated temperature probes is suggested that makes it possible to attain a high linearity in a simple way. Circuitry implementation and techniques that allow one to reduce power supply volta