Výsledky vyhledávání - "V. Govindarajulu"

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

Publikováno v: IEEE Journal of Solid-State Circuits. 37:1421-1432

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS tech

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::736d5cc82f3302f183f8978b5e8bce24
https://doi.org/10.1109/jssc.2002.803944

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1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

Autor: Sriram R. Vangal, Amaresh Pangal, H. Wilson, B. Bloechel, Vasantha Erraguntla, V. Govindarajulu, E. Seligman, Siva G. Narendra, G. Dermer, R. Mooney, Rajendran Nair, A. Keshavarzi, Vivek De, Nitin Borkar, M. Haycock, S. Borkar

Publikováno v: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A router chip, that incorporates on-chip forward body biasing capability with 2% area overhead, achieves 1 GHz operation at 1.1 V supply in a 150 nm logic technology, compared to 1.25 V required for the original design having no body bias. Switching

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f8816032d6e4f6c2e2590e64ec74024d
https://doi.org/10.1109/isscc.2002.993040

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A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

Publikováno v: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

A 32 b integer execution core implements 12 instructions. Circuit and body bias techniques together increase the core clock frequency to 5 GHz. In a 130 nm six-metal dual-V/sub T/ CMOS process, the 2.3 mm/sup 2/ prototype contains 160 k transistors,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::94e0323b4a78816fb2a2f85a7c04cb32
https://doi.org/10.1109/isscc.2002.993107

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Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

Autor: Vivek De, S. Borkar, T. Karnik, V. Govindarajulu, Steven M. Burns, J. Tschanz, Yibin Ye, Nitin Borkar, Liqiong Wei

Publikováno v: 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the op

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a6b1584562e746cac7faf6c4fbcc97d0
https://doi.org/10.1109/vlsic.2002.1015089

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A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

Autor: E. Seligman, V. Govindarajulu, J.D. Prijic, G. Dermer, V. Eriaguntla, Nitin Borkar, Amaresh Pangal, Rajendran Nair, L. Rankin, H. Wilson, Sriram R. Vangal, C.S. Browning

Publikováno v: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that synchronize data through four 1.06 GB/s links, a B-port crossbar, and five point-to-point links of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0244a5ae029eb9bc5d99764740cd7414
https://doi.org/10.1109/isscc.2001.912614

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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Autor: Liqiong Wei, Shekhar Borkar, Tanay Karnik, Yibin Ye, Steven M. Burns, V. Govindarajulu, Vivek De, James W. Tschanz

Publikováno v: DAC

We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2fa36bc87592bf82baca54a94c76f702
https://doi.org/10.1109/dac.2002.1012674

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