Zobrazeno 1 - 10
of 15
pro vyhledávání: '"V. DeJonghe"'
Autor:
C. Fenouillet-Beranger, J. Todeschini, J.C. Le-Denmat, N. Loubet, C. Gallon, P. Perreau, S. Manakli, B. Minghetti, L. Pain, V. Arnal, A. Vandooren, S. Denorme, D. Aime, L. Tosti, C. Savardi, M. Broekaart, P. Gouraud, F. Leverd, V. Dejonghe, P. Brun, M. Guillermet, M. Aminpur, B. Icard, S. Barnola, F. Rouppert, F. Martin, T. Salvetat, S. Lhostis, C. Laviron, N. Auriac, T. Kormann, G. Chabanne, S. Gaillard, F. Boeuf, O. Belmont, E. Laffosse, D. Barge, A. Zauner, A. Tarnowka, K. Romanjec, H. Brut, A. Lagha, S. Bonnetier, F. Joly, J. Coignus, N. Mayet, A. Cathignol, D. Galpin, D. Pop, R. Delsol, R. Pantel, F. Pionnier, G. Thomas, D. Bensahel, S. Deleonibus, O. Faynot, T. Skotnicki, H. Mingam, L. Brevard, C. Buj, C. Soonekindt
Publikováno v:
2007 IEEE International Electron Devices Meeting.
In this paper, we report on FD-SOI with high-k and single metal gate as a possible candidate for the 32 nm LOP and LSTP nodes. Good Ion/Ioff performance for nMOS and pMOS transistors in the ultra-low-leakage regime (Ioff=6.6 pA/μm) are presented. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b01d356319804f33639c8bbcd010bbb
https://doi.org/10.1109/iedm.2007.4418919
https://doi.org/10.1109/iedm.2007.4418919
Autor:
N. Bicais-Lepinay, V. DeJonghe, B. Tavel, M. Jurdit, Stephane Denorme, C. Boccaccio, F. Andre, M. Aminpur, S. Manakli, M. Broekaart, J. Todeschini, C. Laviron, S. Smith, B. Icard, C. Reddy, B. Borot, Nicolas Planes, S. Jullian, Thomas Skotnicki, F. Guyader, Frederic Boeuf, J.P. Jacquemin, P. Morini, J. Bustos, N. Gierczynski, Pascal Gouraud, P. Brun, Franck Arnaud, M. Mellier, F. Salvetti, C. Ortolland, B. Duriez, Laurent Pain
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
This work highlights the realization and 0.248/spl mu/m/sup 2/ to 0.334/spl mu/m/sup 2/ SRAM bit-cells with conventional bulk technology based on 19/spl Aring/ CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd5d5402c851ccecf8dcda10c729bbfe
https://doi.org/10.1109/.2005.1469240
https://doi.org/10.1109/.2005.1469240
Autor:
Daniel Henry, B. Icard, Laurent Pain, S. Manakli, J. Todeschini, Blandine Minghetti, M. Jurdit, V. DeJonghe, V. Wang
Publikováno v:
SPIE Proceedings.
Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments (1,2) . Patterning for sub-45nm node technology requires the development of high performance proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70c26ea6a0c4e561988929488fbfdaba
https://doi.org/10.1117/12.601616
https://doi.org/10.1117/12.601616
Autor:
J. Todeschini, M. Bidaud, J. Rosa, H. Bernard, Franck Arnaud, M. Jurdit, D. Sotta, B. Duriez, J. Grant, Laurent Pain, Thomas Skotnicki, N. Bicais-Lepinay, Pierre Morin, J. Bustos, C. Chaton, Francois Wacquant, R. El-Farhane, Frederic Boeuf, Pascal Gouraud, M.T. Basso, S. Manakli, S. Jullian, V. DeJonghe, B. Tavel, M. Gaillardin
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant Lg=30nm/45nm devices with SiON gate oxide, shallow junctions and process induced strain are demonst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b0c59f4f0efd04c243db59f149ec997
https://doi.org/10.1109/iedm.2004.1419177
https://doi.org/10.1109/iedm.2004.1419177
Autor:
K. Bard, S. Van, Francois Wacquant, H. Achard, P. Spinelli, M. Muller, Roland Pantel, D. Rabilloud, R. Palla, Pierre Morin, V. Tirard, O. Leborgne, Christophe Regnier, E. Olson, D. Ceccarelli, V. DeJonghe, Tushar Mandrekar, V. Carron, B. Froment, V. Gravey, H. Brut, F. Trentesaux, A. Halimaoui, S. Lis, J. Diedrick, Frederic Boeuf, A. Beverina
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
In this work, NiSi SALICIDE has been fully integrated with sub-50 nm gate length transistors and compared to its CoSi/sub 2/ counterpart. Nickel thickness has been reduced to target the CoSi/sub 2/ sheet resistance. It was found that NiSi layers basi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b3a4635456f0e378db88788bfd36555
https://doi.org/10.1109/essderc.2003.1256852
https://doi.org/10.1109/essderc.2003.1256852
Autor:
P.O. Sassoulas, Francois Wacquant, J. Todeschini, M. Woo, M. Charpin, Y. Laplanche, N. Revil, J.C. Oberlin, Roland Pantel, B. Hinschberger, O. Belmont, D. Neira, P. Stolk, Franck Arnaud, M. Broekaart, Frederic Boeuf, I. Guilmeau, D. Ceccarelli, Francois Leverd, N. Emonet, Damien Lenoble, Bertrand Borot, G. Imbert, N. Bicais, S. Delmedico, A. Sicard, Nicolas Planes, J. Farkas, Christophe Regnier, V. Vachellerie, J. Uginet, Chittoor Parthasarathy, E. Denis, V. DeJonghe, Pierre Morin, T. Devoivre, H. Brut, R. Palla, Laurent Pain, P. Vannier, F. Salvetti, A. Beverina, C. Perrot
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f57f1b2bcd5199626774a2f09c78af07
https://doi.org/10.1109/vlsit.2003.1221088
https://doi.org/10.1109/vlsit.2003.1221088
Autor:
M. Denais, J. Todeschini, R.A. Bianchi, Damien Lenoble, Laurent Pain, Y. Laplanche, Franck Arnaud, H. Brut, M. Broekaart, Nicolas Planes, V. Vachellerie, M. Woo, A. Beverina, Pierre Morin, R. Difrenza, Bertrand Borot, C. Perrot, H. Leninger, Francois Wacquant, D. Barge, David Roy, F. Salvetti, D. Ceccarelli, N. Emonet, V. DeJonghe, P. Stolk, B. Tavel, B. Duriez, L. Vishnobulta, I. Guilmeau, Y. Loquet, Frederic Boeuf, T. Devoivre, N. Bicais, J.P. Reynard, M. Jurdit, K. Rochereau, R. Palla, F. Judong, M. Bidaud, P. Vannier, D. Reber
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
A 65nm CMOS platform employing General Purpose (GP) and Low Power (LP) devices and 0.5 /spl mu/m/sup 2/ 6T-SRAM bit-cells was developed using both conventional design and low cost CMOS process flow incorporating a strained silicon solution. Fully wor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ab775f921dd2f959ddab925ffe69424
https://doi.org/10.1109/vlsit.2004.1345363
https://doi.org/10.1109/vlsit.2004.1345363
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.