Zobrazeno 1 - 10
of 78
pro vyhledávání: '"V. De Heyn"'
Autor:
Guillaume Boccardi, Hiroaki Arimura, Roger Loo, Samuel Suhard, Daire J. Cott, Thierry Conard, Naoto Horiguchi, L.-A. Ragnarsson, V. De Heyn, Jerome Mitard, Dan Mocuta, Liesbeth Witters, H. Dekkers, D. H. van Dorp, Nadine Collaert, Kurt Wostyn
Publikováno v:
IEEE Transactions on Electron Devices. 66:5387-5392
This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high- ${k}$ last process. SiO2 dummy gate oxide (D
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1dd5f23cc243b67badeb99d80e2e88e1
https://doi.org/10.1109/ted.2019.2950332
https://doi.org/10.1109/ted.2019.2950332
Autor:
Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, G. Besnard
Publikováno v:
IEEE Transactions on Electron Devices. 65:5165-5171
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92b4a10dc727e8fb50bf8a9778c9db9e
https://doi.org/10.1109/ted.2018.2871265
https://doi.org/10.1109/ted.2018.2871265
Autor:
Jerome Mitard, Frank Holsteyns, Andriy Hikavyy, A. Opdebeeck, Alexey Milenin, Hugo Bender, Dan Mocuta, E. Capogreco, Hiroaki Arimura, Roger Loo, Geert Eneman, Kathy Barla, Farid Sebaai, Niamh Waldron, Kurt Wostyn, E. Dentoni Litta, Clement Porret, Nadine Collaert, Robert Langer, Liesbeth Witters, Andreas Schulze, V. De Heyn, Paola Favia, Christa Vrancken
Publikováno v:
IEEE Transactions on Electron Devices. 65:5145-5150
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5e917791fdccedb5d44a5a1f0844ef9
https://doi.org/10.1109/ted.2018.2871595
https://doi.org/10.1109/ted.2018.2871595
Autor:
Dan Mocuta, E. Chiu, Nadine Collaert, Roger Loo, Robert Langer, A. De Keersgieter, Paola Favia, Liesbeth Witters, Hiroaki Arimura, Frank Holsteyns, Farid Sebaai, Kathy Barla, E. Vancoille, Andreas Schulze, Tom Schram, V. De Heyn, Steven Bilodeau, Andriy Hikavyy, Peter Storck, Jerome Mitard, A. Opdebeeck, Katia Devriendt, Emanuel I. Cooper, Christa Vrancken, Ruben R. Lieten, Geert Eneman, Kurt Wostyn, Alexey Milenin, Niamh Waldron
Publikováno v:
IEEE Transactions on Electron Devices. 64:4587-4593
Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a5c24f4c48574ba63b78514d0463119
https://doi.org/10.1109/ted.2017.2756671
https://doi.org/10.1109/ted.2017.2756671
Autor:
Daire J. Cott, Stephan Brus, K. Kenis, Dan Mocuta, Jerome Mitard, D. H. van Dorp, Nadine Collaert, Hiroaki Arimura, E. Capogreco, Roger Loo, A. Opdebeeck, Guillaume Boccardi, V. De Heyn, L.-A. Ragnarsson, Liesbeth Witters, Kurt Wostyn, Frank Holsteyns, Thierry Conard, Samuel Suhard, Naoto Horiguchi
Publikováno v:
2019 Symposium on VLSI Technology.
We have demonstrated Ge nFinFETs with a record high $\text{G}_{\text{mSA}\Gamma}/\text{SS}_{\text{SAT}}$ and PBTI reliability by improving the RMG high-k last process. The SiO 2 dummy gate oxide (DGO) deposition and removal processes have been identi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::372d860fefbeb4848dc647da0126fe8d
https://doi.org/10.23919/vlsit.2019.8776535
https://doi.org/10.23919/vlsit.2019.8776535
Autor:
A. De Keersgieter, Dan Mocuta, L.-A. Ragnarsson, Daniil Marinov, Robert Langer, E. Dupuy, Roger Loo, Yong Kong Siew, Andriy Hikavyy, G. Mannaert, Anurag Vohra, Liesbeth Witters, Nadine Collaert, Farid Sebaai, V. De Heyn, Hiroaki Arimura, E. Capogreco, Kathy Barla, Christa Vrancken, A. Opdebeeck, F. Holstetns, Steven Demuynck, Naoto Horiguchi, Jerome Mitard, E. Altamirano Sanchez, Clement Porret
Publikováno v:
2019 Symposium on VLSI Technology.
This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb7eec167a5bc03b727e666ffe52f7e9
https://doi.org/10.23919/vlsit.2019.8776558
https://doi.org/10.23919/vlsit.2019.8776558
Autor:
B. Parvais, G. Besnard, T. Zheng, Anne Vandooren, W. Li, Erik Rosseel, Julien Ryckaert, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Nancy Heylen, E. Vecchio, Lan Peng, Juergen Boemmels, Liesbeth Witters, Steven Demuynck, Iuliana Radu, A. Khaled, G. Jamieson, Niamh Waldron, Philippe Matagne, Nouredine Rassoul, V. De Heyn, Amey Mahadev Walke, Gweltaz Gaudin, Walter Schwarzenbach, D. Radisic, Z. Wu, Katia Devriendt, Haroen Debruyn, Fumihiro Inoue, Bich-Yen Nguyen, Andriy Hikavyy, W. Vanherle, J. Franco, Lieve Teugels
Publikováno v:
2019 Symposium on VLSI Technology.
3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::19cefb6cbd6e3debff3f332f344f1440
https://doi.org/10.23919/vlsit.2019.8776490
https://doi.org/10.23919/vlsit.2019.8776490
Autor:
J. Franco, Daire J. Cott, Guido Groeseneken, Lars-Ake Ragnarsson, Gerhard Rzepa, Tibor Grasser, Anne Vandooren, Z. Wu, Julien Ryckaert, Nadine Collaert, Hiroaki Arimura, B. Kaczer, Naoto Horiguchi, V. De Heyn, Geert Hellings, D. Linten, Stephan Brus
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate two strategies to tolerate the inheren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cac7cfe23ffaae1f82482046a982ae93
https://doi.org/10.1109/iedm.2018.8614559
https://doi.org/10.1109/iedm.2018.8614559
Autor:
Liesbeth Witters, Z. Wu, Anne Vandooren, G. Mannaert, Nadine Collaert, E. Vecchio, Lars-Ake Ragnarsson, Romain Ritzenthaler, Niamh Waldron, V. De Heyn, Jerome Mitard, Nouredine Rassoul, Boon Teik Chan, Dan Mocuta, Bertrand Parvais, Veeresh Deshpande, Fumihiro Inoue, Lan Peng, Andriy Hikavyy, G. Jamieson, J. Franco, W. Vanherle, Lieve Teugels, T. Zheng, W. Li, Amey Mahadev Walke, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Nancy Heylen, Steven Demuynck, Geert Hellings, Juergen Boemmels
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device densit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b551e755a64818bb006da801ed01452
https://doi.org/10.1109/iedm.2018.8614654
https://doi.org/10.1109/iedm.2018.8614654
Autor:
Iuliana Radu, Anne Vandooren, T. Zheng, W. Li, Fumihiro Inoue, Niamh Waldron, J. Franco, Andriy Hikavyy, Liesbeth Witters, Nouredine Rassoul, Lieve Teugels, W. Vanherle, E. Vecchio, Nadine Collaert, G. Verbinnen, Bertrand Parvais, V. De Heyn, G. Besnard, F. M. Bufler, B.-Y. Nguyen, Lan Peng, Boon Teik Chan, Dan Mocuta, W. Schwarzenbach, Katia Devriendt, Romain Ritzenthaler, G. Jamieson, Erik Rosseel, Geert Hellings, G. Gaudin, V. Desphande, Nancy Heylen, Amey Mahadev Walke, Z. Wu
3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0ee461fd85f0874b4d632f9267f8b128
https://doi.org/10.1109/vlsit.2018.8510705
https://doi.org/10.1109/vlsit.2018.8510705
