Zobrazeno 1 - 10
of 37
pro vyhledávání: '"V. Chikarmane"'
Autor:
Minh-Tam N. Pham, Michael C. Haffner, Heather C. Wick, Jonathan B. Coulter, Anuj Gupta, Roshan V. Chikarmane, Harshath Gupta, Sarah Wheelan, William G. Nelson, Srinivasan Yegnasubramanian
Publikováno v:
Cancer Research. 82:680-680
Prostate cancer (PCa) is the most common malignancy and second leading cause of cancer death in American men. Androgen Receptor (AR) mediated transcriptional program is central to normal prostate homeostasis and drives PCa growth and survival. Chromo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f276303bc6edd367a9c52370990d93df
https://doi.org/10.1158/1538-7445.am2022-680
https://doi.org/10.1158/1538-7445.am2022-680
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fa7cc3fb3c8d31dc8c2da50fdf17147
https://doi.org/10.1109/iitc.2018.8430489
https://doi.org/10.1109/iitc.2018.8430489
Autor:
V. Chikarmane, M. Hattendorf, S. Kosaraju, Abdur Rahman, M. Sprinkle, A. Tura, V. Sharma, G. Leatherman, H. Gomez, G. Ding, D. Towner, P. Sinha, C. Auth, S. Jaloviar, J. Birdsall, I. Post, B. Ho, D. Bergstrom, J. Leib, K. Lee, T. Mule, D. Hanken, M. Asoro, A. Saha, M. Sharma, C. Pelto, H. Meyer, M. Prince, L. Pipes, C. Staus, J. Shin, R. Heussner, S. Parthasarathy, C. Parker, V. Bhagwat, C. Ward, J. Dacuna Santos, M. Buehler, H. Hiramatsu, R. Suri, A. Aliyarukunju, M. Haran, S. Rajamani, A. Tripathi, P. Smith, A. Madhavan, W. Han, A. Yeoh, N. Bisnik, K. Marla, S. Joshi, H. Kothari, Q. Fu, I. Jin, S. Kirby, A. St. Amour
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local interconnect layers is described. For high density, a novel self-al
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbb1a928dda6105043b499935aa12901
https://doi.org/10.1109/iedm.2017.8268472
https://doi.org/10.1109/iedm.2017.8268472
Autor:
Patel Reken, P. Plekhanov, S. Rajamani, P. Reese, Conor P. Puls, Muhammet Uncuer, Rahim Kasim, E. Hwang, M. Agostinelli, M. Bost, Swaminathan Sivakumar, S. Nigam, Sanjay Natarajan, P. Charvat, S. Kosaraju, M. Prince, D. Rao, B. Song, M. Yang, S. Williams, P. Yashar, K. S. Lee, Pulkit Jain, I. Jin, Q. Fu, H. Hiramatsu, Kevin J. Fischer, Max M. Heckscher, R. McFadden, V. Chikarmane, Haran Mohit K, A. Rosenbaum, Huichu Liu, D. Bahr, C. Ganpule, C. Pelto, C. Allen
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5878d1ee61e8d33e2cf853ee2454b701
https://doi.org/10.1109/iitc-mam.2015.7325600
https://doi.org/10.1109/iitc-mam.2015.7325600
Autor:
K. Fischer, Pulkit Jain, Sell Bernhard, P. Plekhanov, Swaminathan Sivakumar, S. Rajamani, R. James, Mark Y. Liu, C. Kenyon, L. Neiberg, Pete Smith, J. Wiedemer, M. Haran, M. Prince, Kevin Zhang, A. Bowonder, S. Morarka, R. Mehandru, B. Song, M. Agostinelli, Q. Fu, Y. Luo, W. Han, M. Heckscher, R. Grover, R. Patel, V. Chikarmane, S. Akbar, S. Chouksey, P. Patel, D. Hanken, I. Jin, L. Pipes, C. Parker, J. Sandford, M. Giles, Paul A. Packan, Tahir Ghani, A. Paliwal, E. Haralson, M. Bost, K. Tone, Sanjay Natarajan, M. Yang, Eric Karl, Hei Kam, R. Jhaveri, R. Heussner, T. Troeger, A. Dasgupta, S. Govindaraju, C. Pelto
Publikováno v:
2014 IEEE International Electron Devices Meeting.
A 14nm logic technology using 2nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a3dec100c56e7fcbb7cfef517ecf3b6
https://doi.org/10.1109/iedm.2014.7046976
https://doi.org/10.1109/iedm.2014.7046976
Autor:
Christopher D. Thomas, Michael L. Hattendorf, Mark R. Brazier, K. Zawadzki, R. McFadden, P. Hentges, J. Seiple, W. Han, D. Ingerly, S. Jaloviar, Cory E. Weber, Huichu Liu, Robert James, C. Auth, C. Parker, Kaizad Mistry, M. Prince, V. Chikarmane, S. Ramey, J. Neirynck, A. Blattner, J. Roesler, M. Bost, P. Yashar, D. Hanken, J. Jopling, Ian R. Post, B. McIntyre, C. Kenyon, T. Troeger, S. Pradhan, Pulkit Jain, D. Towner, C. Allen, David Jones, J. Hicks, Timothy E. Glassman, J. Sandford, L. Pipes, R. Heussner, T. Reynolds, M. Buehler, Daniel B. Bergstrom, Tahir Ghani, Pete Smith, R. Grover, Subhash M. Joshi
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resultin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12d26eb034c9068558a075df1316c3c7
https://doi.org/10.1109/vlsit.2012.6242496
https://doi.org/10.1109/vlsit.2012.6242496
Autor:
C. Ege, A. Agrawal, A. Schmitz, A. Kandas, T. Mule, M. Buehler, D. Rao, J. Hicks, P. Parthangal, David Jones, P. Yashar, R. McFadden, Kaizad Mistry, R. Ascazubi, V. Chikarmane, K. S. Lee, N. Speer, J. Roesler, C. Ganpule, Guotao Wang, D. Ingerly, Timothy E. Glassman, R. Grover, A. Blattner, Y. Shusterman, Manvi Sharma, H. Khan, A. Madhavan, N. Lazo, P. Tiwari, P. Hentges, J. Shin, D. Parsons, Sudarshan Rangaraj, H. Liu, B. Choudhury, F. Cinnor
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c76256ec386ece7a609902e2d6a446d
https://doi.org/10.1109/iitc.2012.6251663
https://doi.org/10.1109/iitc.2012.6251663
Autor:
Robert M. Bigwood, J. Neirynck, V. Chikarmane, Michael A. Childs, Yeoh Andrew W, J. Neulinger, Y. Neirynck, D. Becher, J. Choi, P. Plekhanov, P. Yashar, M. Weiss, B. McFadden, G. Malyavantham, S. Klopcic, F. Xia, Jun He, Y. Shusterman, Saurabh Agrawal, S. Williams, S. Daviess, T. Van, C. Ganpule, Ruth A. Brain, C. Pelto, P. Hentges, I. Jin, M. Buehler
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7426bfd607ab2178c02069a496293925
https://doi.org/10.1109/iitc.2009.5090400
https://doi.org/10.1109/iitc.2009.5090400
Autor:
S. Lodha, J. Seiple, T. Troeger, S. Pae, G. Ding, Tahir Ghani, I. Jin, L. Pipes, C.-H. Chang, Ruth A. Brain, Cory E. Weber, Jun He, Kevin Zhang, Paul A. Packan, Robert James, R. Heussner, Seung Hwan Lee, S. Klopcic, W. Han, Anand Portland Murthy, Michael A. Childs, K. Dev, J. Neirynck, Mark Y. Liu, J. Sebastian, B. McFadden, Oleg Golonzka, Swaminathan Sivakumar, V. Chikarmane, C. Pelto, H. Deshpande, Sanjay Natarajan, Mark Armstrong, M. Yang, L. Neiberg, Mark R. Brazier, B. Song, Yeoh Andrew W, C. Parker, C. Kenyon, M. Bost, K. Tone, Sell Bernhard
Publikováno v:
2008 IEEE International Electron Devices Meeting.
A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e61e7413da3a7648aaa6f2eabc4f37c
https://doi.org/10.1109/iedm.2008.4796777
https://doi.org/10.1109/iedm.2008.4796777
Autor:
K. Lee, S. Haight, P. Yashar, S. Williams, P. Moon, H. Liu, R. Grover, S. Sattiraju, S. Agraharam, D. Becher, M. Goodner, S. Nolen, P. Ramanarayanan, K. Fischer, N. Patel, D. Ingerly, T. Ibrahim, T. Mule, T. Schroeder, E. Mays, S. Pradhan, C. Litteken, H. Kothari, Jun He, V. Chikarmane, S. Joshi, Y. Lin, J. Robinson
Publikováno v:
2008 International Interconnect Technology Conference.
Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ba40596c5164385e6d5b22598af8c29
https://doi.org/10.1109/iitc.2008.4546971
https://doi.org/10.1109/iitc.2008.4546971