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pro vyhledávání: '"V. Aravinda Rajan"'
Autor:
Jyotsnarani Tripathy, M. Balasubramani, V. Aravinda Rajan, Vimalathithan S, Anurag Aeron, Meena Arora
Publikováno v:
Measurement: Sensors, Vol 33, Iss , Pp 101151- (2024)
Many countries have seen a steady increase in lifetime duration through the past many years as a result of notable advancements in ecological and individual cleanliness, general health, including healthcare. Hence, it is anticipated that rising life
Externí odkaz:
https://doaj.org/article/b8dd80620d5148159ba5c3994d1b8ebb
Publikováno v:
Second International Conference on Computer Networks and Communication Technologies ISBN: 9783030370503
The Internet of Things (IoT) ML and AI is an enormous gathering of gadgets containing sensors or actuators associated together over wired or remote systems. With a gauge of more than 25 billion gadgets associated together by 2020, IoT using ML and AI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ea3d8eabea6869560b54d3c095a42d5
https://doi.org/10.1007/978-3-030-37051-0_89
https://doi.org/10.1007/978-3-030-37051-0_89
FPSMM : Fuzzy probabilistic based semi morkov model among the sensor nodes for realtime applications
Publikováno v:
2017 International Conference on Intelligent Sustainable Systems (ICISS).
Emerging technology in terms of hardware and software over wireless sensor network result in various applications The main limitation of sensor nodes are less life span, more energy consumption. Many papers has explained about the stochastic model bu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2463642c0446ad03dd1bab3d55bdc35d
https://doi.org/10.1109/iss1.2017.8389391
https://doi.org/10.1109/iss1.2017.8389391
Publikováno v:
2015 2nd International Conference on Electronics and Communication Systems (ICECS).
The Clock gating reduces dynamic power dissipation in synchronous circuits. The gating function is the process of filtering glitches from a block which is achieved by inserting clock gating cell. Clock gating logic uses strong and weak matching proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9cdc767f13ed66fdae02e3cc8f1ace0
https://doi.org/10.1109/ecs.2015.7125063
https://doi.org/10.1109/ecs.2015.7125063
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