Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

Autor: T. Mota Frutuoso, X. Garros, P. Batude, L. Brunet, J. Lacord, B. Sklenard, V. Lapras, C. Fenouillet-Beranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, E. Catapano, M. Casse, J. Lugo-Alvarez, P. Ferrari, F. Gaillard

Publikováno v: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022)
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Jun 2022, Honolulu (HI), United States. ⟨10.1109/VLSITechnologyandCir46769.2022.9830504⟩
IEEELink

International audience; We present, for the first time, a new CV based technique to extract the Active Dopant Profile under the spacer in thin film FDSOI devices (CV-AJP). The methodology is successfully applied to FDSOI devices fabricated at 500°C

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9eef2750dbb3aeee813a581581b63000
https://hal.science/hal-04069091

Opportunities and challenges brought by 3D-sequential integration

Autor: Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone

Publikováno v: 2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018

Cytological features and nuclear scores: Diagnostic tools in preoperative fine needle aspiration of indeterminate thyroid nodules with RAS or BRAF K601E mutations?

Autor: Marie-Laure Denier, Joris Giai, Lucie Ravella, M. Decaussin-Petrucci, Jonathan Lopez, V. Lapras, Françoise Descotes, Françoise Borson-Chazot, Jean-Christophe Lifante

Publikováno v: Cytopathology
Cytopathology, 2021, 32 (1), pp.37-44. ⟨10.1111/cyt.12904⟩

INTRODUCTION The cytological diagnosis of follicular-patterned thyroid lesions is challenging, especially since the World Health Organisation classification has recognised non-invasive follicular thyroid neoplasm with papillary-like features. These e

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::40a9f0175a7e7ea4c83e3122ef07e81a
https://pubmed.ncbi.nlm.nih.gov/32803788

Confined selective lateral epitaxial growth of 16-nm thick Ge nanostructures on SOI substrates: Advantages and challenges

Autor: Rami Khazaka, Y. Bogumilowicz, Bernard Previtali, Sylvain David, Denis Rouchon, Nicolas Chevalier, Sylvain Maitrejean, Zdenek Chalupa, Hervé Boutry, Anne Marie Papon, V. Lapras

Publikováno v: Applied Surface Science
Applied Surface Science, Elsevier, 2018, 445, pp.77-80. ⟨10.1016/j.apsusc.2018.03.104⟩
Applied Surface Science, 2018, 445, pp.77-80. ⟨10.1016/j.apsusc.2018.03.104⟩

In this contribution, we report on the growth of Ge inside extremely thin 16-nm thick cavities through selective lateral growth of Ge on 300 mm silicon-on-insulator (0 0 1) substrates. We showed that the density of defects depends on the cavity shape

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4466803858aeb20876c6e277df144280
https://doi.org/10.1016/j.apsusc.2018.03.104

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

Autor: Maud Vinet, Virginie Loup, Bernard Previtali, G. Audoit, Vincent Delaye, V. Lapras, Mikael Casse, Joris Lacord, Sylvain Barraud, Thomas Ernst, Nicolas Bernier, N. Rambal, Olivier Rozeau, V. Balan, L. Dourthe, Zdenek Chalupa, A. Jannaud, Sebastien Martinie, C. Vizioz, J.M. Hartmann, G. Romano

Publikováno v: 2018 IEEE International Electron Devices Meeting (IEDM).

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0655b963a78cafb62cfba4ac52ba9005
https://doi.org/10.1109/iedm.2018.8614507