Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Víctor Viñals-Yufera"'
Publikováno v:
PLoS ONE, Vol 19, Iss 5, p e0303712 (2024)
[This corrects the article DOI: 10.1371/journal.pone.0220135.].
Externí odkaz:
https://doaj.org/article/a86ffe096a7c4ee085d6a78485a866a6
Autor:
Marta Ortín-Obón, Andrea Peano, Mahdi Tala, Marco Balboni, Luca Ramini, Nonato Maddalena, Víctor Viñals-Yufera, Davide Bertozzi
Publikováno v:
Photonic Interconnects for Computing Systems ISBN: 9781003339076
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cf35c246106b66b25573f3b13621908c
http://hdl.handle.net/11392/2392187
http://hdl.handle.net/11392/2392187
Autor:
Pablo Enrique Ibáñez Marín, Víctor Viñals Yufera, Enrique Fermín Torres Moreno, Jose M. Llaberia
Publikováno v:
ISCA
This paper focuses on how to design a Store Buffer (STB) well suited to first-level multibanked data caches. Our goal is to forward data from in-flight stores to dependent loads with the latency of a cache bank. For that we propose a particular two-l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f788eda1ff23208cfae97f1f70c3da9d
https://doi.org/10.1145/1080695.1070009
https://doi.org/10.1145/1080695.1070009
Publikováno v:
IEEE Access, Vol 8, Pp 192379-192392 (2020)
Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in orde
Externí odkaz:
https://doaj.org/article/68ada3df74354463ade76464f7a179d6
Publikováno v:
PLoS ONE, Vol 14, Iss 8, p e0220135 (2019)
SPEC CPU is one of the most common benchmark suites used in computer architecture research. CPU2017 has recently been released to replace CPU2006. In this paper we present a detailed evaluation of the memory hierarchy performance for both the CPU2006
Externí odkaz:
https://doaj.org/article/ee447af594c84d358e58a4eefd929e7a
Autor:
Alba Pedro-Zapater, Clemente Rodríguez, Juan Segarra, Rubén Gran Tejero, Víctor Viñals-Yúfera
Publikováno v:
Mathematics, Vol 8, Iss 2, p 184 (2020)
Matrix transposition is a fundamental operation, but it may present a very low and hardly predictable data cache hit ratio for large matrices. Safe (worst-case) hit ratio predictability is required in real-time systems. In this paper, we obtain the r
Externí odkaz:
https://doaj.org/article/48838d70bce64484a73455915d0935e4
Publikováno v:
ResearcherID
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::24c96c8e05cc71f22856450ea039c553
http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000354965500241&KeyUID=WOS:000354965500241
http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000354965500241&KeyUID=WOS:000354965500241