Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Uwe Paul Schroeder"'
Publikováno v:
DTCO and Computational Patterning II.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13bcd1ff869bd72b2e5849419d6c4002
https://doi.org/10.1117/12.2657156
https://doi.org/10.1117/12.2657156
Publikováno v:
DTCO and Computational Patterning II.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3e70f40fbc60432a3b543006f2901ca
https://doi.org/10.1117/12.2659397
https://doi.org/10.1117/12.2659397
Autor:
Lynn T. N. Wang, Klaus-Peter Johnsen, Ivan Tanev, Fadi Batarseh, Chang Su, Pouya Rezaeifakhr, Uwe Paul Schroeder
Publikováno v:
DTCO and Computational Patterning II.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea2ee437179c5938d9cd6e589f249426
https://doi.org/10.1117/12.2658646
https://doi.org/10.1117/12.2658646
Autor:
Jonathan Fales, Binod Kumar G. Nair, Jeffrey E. Nelson, Frank E. Gennari, Philippe Hurat, Jac Condella, Akif Sultan, Aaron Sinnott, Xiaoyuan Qi, Sriram Madhavan, Uwe Paul Schroeder, Rwik Sengupta, Ya-Chieh Lai
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 34:372-378
A novel foundry yield model for integrated circuit products has been developed based on critical area scaling. The newly proposed model does not need the information of the defect density by failure mode. This has considerably simplified the model in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af3a410dc43ec2c38e5a4f8fa21d4d4b
https://doi.org/10.1109/tsm.2021.3075650
https://doi.org/10.1109/tsm.2021.3075650
Autor:
Lynn T. N. Wang, Uwe Paul Schroeder, Punitha Selvam, Fadi Salameh Batarseh, Pouya Rezaeifakhr, Ariel de Jesus Reyes Ruiz, Teodora Nicolae, Ivan Tanev, Sriram Madhavan
Publikováno v:
DTCO and Computational Patterning.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0294b0817b7f623bad62e21463b51049
https://doi.org/10.1117/12.2614460
https://doi.org/10.1117/12.2614460
Autor:
Fadi Salameh Batarseh, Uwe Paul Schroeder, Jeff Nelson, Piyush Pathak, Wei-Long Wang, Ya-Chieh Lai
Publikováno v:
DTCO and Computational Patterning.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c39c51395aa20f214d9c1e1aabc2cfe
https://doi.org/10.1117/12.2617261
https://doi.org/10.1117/12.2617261
Autor:
Suraag S. Tellakula, Uwe Paul Schroeder, Janam Bakshi, Punitha Selvam, Pouya Rezaeifakhr, Sriram Madhavan
Publikováno v:
DTCO and Computational Patterning.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03781103a9108b123ccf1e2d6ffa9f09
https://doi.org/10.1117/12.2613828
https://doi.org/10.1117/12.2613828
Autor:
Piyush Pathak, Uwe Paul Schroeder, Fadi Batarseh, Philippe Hurat, Jeffrey E. Nelson, Sriram Madhavan, Ya-Chieh Lai
Publikováno v:
Design-Process-Technology Co-optimization XV.
Two-dimensional pattern matching libraries are used to define known hotspots in the design space. These libraries can then be integrated into a physical design router to search and fix such hotspots prior to the design being completed and signed off.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::40d43d18d5b04c9fb948289250bf8f06
https://doi.org/10.1117/12.2586112
https://doi.org/10.1117/12.2586112
Publikováno v:
Design-Process-Technology Co-optimization XV.
Critical Area Analysis (CAA) is an established DFM tool to assess the defect limited yield of a semiconductor design. However, several factors limit the usefulness of this tool for advanced technology nodes at 28nm and below. Specifically for metal d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::701933d88c550ab1201adeee3db97e3f
https://doi.org/10.1117/12.2582844
https://doi.org/10.1117/12.2582844
Autor:
Rais Huda, Zhao Chuan Lee, Sriram Madhavan, Michael Simcoe, Uwe Paul Schroeder, Vikas Mehrotra, Lynn T.-N. Wang, Mckay Thomas G
Publikováno v:
Design-Process-Technology Co-optimization XV.
Electrical Design-for-Manufacturability (DFM) checks are developed to quantify layout enhancements and their impact on circuit performance for analog designs. A database containing circuit topologies of analog matched devices is built. Then, connecti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c94d00d01d3ce407d3ceaba4c9dfc59
https://doi.org/10.1117/12.2583839
https://doi.org/10.1117/12.2583839