Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Utku Diril"'
Autor:
Kim Hazelwood, Hsien-Hsin S. Lee, Bill Jia, Liu Ke, David Brooks, Martin Schatz, Maxim Naumov, Xuan Zhang, Benjamin Youngjae Cho, Carole-Jean Wu, Bert Maher, Amin Firoozshahian, Meng Li, Mark Hempstead, Utku Diril, Brandon Reagen, Mikhail Smelyanskiy, Vikas Chandra, Xiaodong Wang, Udit Gupta, Dheevatsa Mudigere
Publikováno v:
ISCA
Personalized recommendation systems leverage deep learning models and account for the majority of data center AI cycles. Their performance is dominated by memory-bound sparse embedding operations with unique irregular memory access patterns that pose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::421f7b2188846753693aa1f8fa12cf0f
Autor:
Misha Smelyanskiy, Pieter Noordhuis, Bill Jia, Soumith Chintala, Jason Lu, Kim Hazelwood, Xiaodong Wang, Dmytro Dzhulgakov, Sarah Bird, Mohamed Fawzy, Aditya Kalro, Utku Diril, Liang Xiong, Kevin M. Lee, David Brooks, James Law, Yangqing Jia
Publikováno v:
HPCA
Machine learning sits at the core of many essential products and services at Facebook. This paper describes the hardware and software infrastructure that supports machine learning at global scale. Facebook's machine learning workloads are extremely d
Publikováno v:
Journal of Electronic Testing. 24:129-141
Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations
Publikováno v:
Journal of Low Power Electronics. 3:78-95
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:514-524
Nanometer circuits are becoming increasingly susceptible to soft errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming cruci
Publikováno v:
VLSI Design
Usage of dual supply voltages in a digital circuit is an effective way of reducing the dynamic power consumption due to the quadratic relation of supply voltage to dynamic power consumption. But the need for level shifters when a low voltage gate dri
Publikováno v:
Journal of Low Power Electronics. 1:145-152
Publikováno v:
VLSI Design
As technology scales to 40nm and beyond, intra-die process variability causes large delay and leakage variations across a chip in addition to expected die-to-die variations. In this paper, a new approach to post-manufacture circuit adaptation for yie
Publikováno v:
DATE
Design, Automation, and Test in Europe ISBN: 9781402064876
Design, Automation, and Test in Europe ISBN: 9781402064876
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming cruci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d6ca6610e90d56698f9ad42f0f3a59db
Publikováno v:
DFT
We present adaptive design techniques that compensate for manufacturing induced process variations in Deep Sub-micron (DSM) Integrated Circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design