Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Ushasree Katakamsetty"'
Autor:
Ushasree Katakamsetty, Stefan Nikolaev Voykov, Boris Vasilev, Sam Nakagawa, Tamba Tugbawa, Jansen Chee, Aaron Gower-Hall, Brian Lee, Weiyang Zhu, Bifeng Li, Kimiko Ichikawa
Publikováno v:
2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9d730bb1c08d2a22fd6f99ff721d780
https://doi.org/10.1109/edtm55494.2023.10103106
https://doi.org/10.1109/edtm55494.2023.10103106
Autor:
Ushasree Katakamsetty, Stefan Voykov, Sascha Bott, Sam Nakagawa, Tamba Gbondo-Tugbawa, Aaron Gower-Hall, Brian Lee, Jansen Chee, Henry Geng, Weiyang Zhu, Bifeng Li, Kimiko Ichikawa
Publikováno v:
DTCO and Computational Patterning.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa0403ec439f4f9c2637c0ee6e7a789e
https://doi.org/10.1117/12.2616078
https://doi.org/10.1117/12.2616078
Autor:
Jeff Wilson, Ruben Ghulghazaryan, Ernesto Gene de la Garza, Sam Nakagawa, Ushasree Katakamsetty, D.G. Piliposyan, Simon Favre
Publikováno v:
Design-Process-Technology Co-optimization XV.
In semiconductor manufacturing, intellectual property (IP) cores/blocks play a dominant role in modern chip design. The driving factor for IP usage is the time-to-market benefit delivered through design reuse. Today, IP blocks include the entire rang
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd812caf307bb86bc0d56e85c0fe7338
https://doi.org/10.1117/12.2585488
https://doi.org/10.1117/12.2585488
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
Chemical mechanical polishing (CMP) is a critical process in Integrated Circuit (IC) manufacturing used to ensure planarity of the layers which comprise the IC. The IC design and CMP process must be optimally integrated otherwise dishing and erosion
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4622023f5c6fee9aea51a60f597f9d7e
https://doi.org/10.1117/12.2514467
https://doi.org/10.1117/12.2514467
Autor:
Ramasamy Chockalingam, Li Han Chen, Qian Chen, Ushasree Katakamsetty, Lanfei Xie, Juan Boon Tan, Xiaochong Guan, Chee Wee Eng, Soon Yoeng Tan, Li Pinghui
Publikováno v:
2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Ahstract- Multi-level Metal-Oxide-Metal Capacitors (MOM) is widely utilized in CMOS process. It is an inter-digitated three dimensional multi-level finger capacitor structure formed in dual damascene copper metal layers in the Back-end-of-Line (BEOL)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00afe0d523e653eaf8d49a245b17788f
https://doi.org/10.1109/ipfa.2018.8452535
https://doi.org/10.1109/ipfa.2018.8452535
Autor:
Rod Augur, Dewei Xu, Ravi Prakash Srivastava, Hyung Woo Kim, Ushasree Katakamsetty, Ernesto Gene de la Garza, Robert Fox
Publikováno v:
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
R (line resistance) and C (coupling capacitance) parameters are among the critical parameter list or even wafer acceptance criteria in volume production. Process engineers rely on R and C monitoring macros to tune processes to meet targets and contro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96c8d534cba99a1317970ee5bb38969e
https://doi.org/10.1109/asmc.2018.8373150
https://doi.org/10.1109/asmc.2018.8373150
Autor:
Yongfu Li, Jiansheng Jansen Chee, Chiu Wing Hui, Ushasree Katakamsetty, Ernesto Gene de la Garza, Yaodong Huang
Publikováno v:
SPIE Proceedings.
As process technology scales down, the number of Chemical Mechanical Polishing (CMP) processes and steps used in chip manufacturing are increasing exponentially. Shrinking process margins increase the risk of excessive metal or oxide thickness or top
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9636f1eb09dd875fe2b81af252ec2a54
https://doi.org/10.1117/12.2262076
https://doi.org/10.1117/12.2262076
Autor:
Tamba Gbondo-Tugbawa, Ushasree Katakamsetty, Brian Lee, Kuang-Han Chen, Yongfu Li, Jaime Bravo, Aaron Gower-Hall, Sang Min Han, Jansen Chee, Colin Hui
Publikováno v:
SPIE Proceedings.
As we move to advanced technology nodes, the requirements on within chip and across wafer planarity are becoming more demanding [1]. Also, the number of Chemical Mechanical Polishing (CMP) processes and steps used in microelectronic chip manufacturin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::153c0293f8e0cb85fc2e7965471f09aa
https://doi.org/10.1117/12.2219545
https://doi.org/10.1117/12.2219545
Publikováno v:
SPIE Proceedings.
OPC Verification is important to identify the critical wafer hotspots prior to mask fabrication. It helps to identify process limiting structures and possible yield limiters. These hotspots are also used by litho engineers to set up process condition
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4906c52961bef83f2f613bb23c678e06
https://doi.org/10.1117/12.2196646
https://doi.org/10.1117/12.2196646
Publikováno v:
SPIE Proceedings.
DFM rule based scoring is associated with manufacturability rules checking and applying the scoring to predict the yield entitlement for an IC chip design. Achieving high DFM score is one of the key requirements to get high yield. The DFM scoring met
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::202f0f84406c2a2a2e5119b728e74238
https://doi.org/10.1117/12.2085733
https://doi.org/10.1117/12.2085733