Zobrazeno 1 - 10
of 49
pro vyhledávání: '"Uri Weiser"'
Publikováno v:
IEEE Computer Architecture Letters. 22:49-52
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 16:1-27
Memory prefetchers are designed to identify and prefetch specific access patterns, including spatiotemporal locality (e.g., strides, streams), recurring patterns (e.g., varying strides, temporal correlation), and specific irregular patterns (e.g., po
Publikováno v:
IEEE Computer Architecture Letters. 18:99-102
Systolic arrays (SAs) are highly parallel pipelined structures capable of executing various tasks such as matrix multiplication and convolution. They comprise a grid of usually homogeneous processing units (PUs) that are responsible for the multiply-
Autor:
Uri Weiser, Gil Shomron
Publikováno v:
MICRO
Deep neural networks (DNNs) are known for their inability to utilize underlying hardware resources due to hardware susceptibility to sparse activations and weights. Even in finer granularities, many of the non-zero values hold a portion of zero-value
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::082bdb732349401bdb70f0a41ed22d58
http://arxiv.org/abs/2004.09309
http://arxiv.org/abs/2004.09309
Publikováno v:
Computer Vision – ECCV 2020 ISBN: 9783030586065
ECCV (10)
ECCV (10)
Convolutional neural networks (CNNs) introduce state-of-the-art results for various tasks with the price of high computational demands. Inspired by the observation that spatial correlation exists in CNN output feature maps (ofms), we propose a method
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a832064b8de5fb6d2a1767eb596015c
https://doi.org/10.1007/978-3-030-58607-2_14
https://doi.org/10.1007/978-3-030-58607-2_14
Publikováno v:
IEEE Computer Architecture Letters. 16:141-144
Hardwired dynamic NAND address decoders are widely used in random access memories to decode parts of the address. Replacing wires by resistive elements allows storing and reprogramming the addresses and matching them to an input address. The resistiv
Publikováno v:
IEEE Computer Architecture Letters. 16:68-71
Memory hierarchies in modern computing systems work well for workloads that exhibit temporal data locality. Data that is accessed frequently is brought closer to the computing cores, allowing faster access times, higher bandwidth, and reduced transmi
Publikováno v:
Computer. 49:47-55
By scheduling each workload according to its most advantageous core and managing voltage and frequency, the heterogeneous energy-aware race to halt (H-EARtH) algorithm optimizes CPU platform energy.
Publikováno v:
Journal of Parallel and Distributed Computing. 95:3-14
Additional transistors available in each process generation are used to increase the number of cores on chip. This trend results in high execution unit performance relative to other available resources, such as memory bandwidth, I/O bandwidth, and po
Autor:
Uri Weiser
Publikováno v:
IEEE Micro. 37:126-128
Uri Weiser, recipient of the 2016 ACM-IEEE Computer Society Eckert-Mauchly Award, shares insights from his career of nearly 40 years in the computer architecture field.