Zobrazeno 1 - 10
of 264
pro vyhledávání: '"Underclocking"'
Publikováno v:
Electronics
Volume 10
Issue 7
Electronics, Vol 10, Iss 775, p 775 (2021)
Volume 10
Issue 7
Electronics, Vol 10, Iss 775, p 775 (2021)
At the heart of most technological advancements is a network of processors executing code and consuming energy. Understanding those systems’ energy consumption profiles provides optimisation possibilities and thus contributes to strategies for redu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::21ad43ee81e1299976d2023a90859de1
Publikováno v:
NOCS
The performance of graphics processing units (GPU) workloads can be sensitive to the various clock domains which are dynamically tunable in modern GPUs. In this work, we observe that GPU application performance is sensitive towards NoC clock frequenc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81936e7a8df88295e4b5303b59f1ae44
https://doi.org/10.1145/3479876.3481590
https://doi.org/10.1145/3479876.3481590
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9789811578038
Fault injection attacks pose serious threat in security of embedded devices since they require less expertise to conduct them. Suitable countermeasures can only be built if there effects are studied and analyzed in detail. This paper presents circuit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d574a45f9f2428d959d4c9ff1b1d7d9b
https://doi.org/10.1007/978-981-15-7804-5_3
https://doi.org/10.1007/978-981-15-7804-5_3
Autor:
Riadul Islam, Matthew R. Guthaus
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:1054-1062
In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2483470ac0d286ad364071a102d8d925
https://doi.org/10.1109/tvlsi.2016.2605580
https://doi.org/10.1109/tvlsi.2016.2605580
Publikováno v:
2019 11th International Conference on Electrical and Electronics Engineering (ELECO).
In this study, we will explain what settings the RX580 4GB AMD graphics card should be operated for in order to be able to perform Ethereum and Monero mining at high speed and with less energy consumption. Core and memory undervolting, core undercloc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2b1120769e0fb93452acc2e593c18565
https://doi.org/10.23919/eleco47770.2019.8990483
https://doi.org/10.23919/eleco47770.2019.8990483
Akademický článek
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Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:3080-3093
A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd790ba576bfdc16509d7d996c7f6477
https://doi.org/10.1109/tvlsi.2016.2539926
https://doi.org/10.1109/tvlsi.2016.2539926
Autor:
Vandana Prajapati, Uday Panwar
Publikováno v:
International Journal of Computer Applications. 143:23-27
dissipation is major drawback in the digital sequential circuit design of low power electronic devices. Clock signal is one input which is common for all the sequential circuits. The clock signal has major power dissipation at high frequencies. The c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d778fd2e70237bf771501db5b6e59c8
https://doi.org/10.5120/ijca2016910202
https://doi.org/10.5120/ijca2016910202
Autor:
Kanchana Bhaaskaran Vettuvanam Somasundaram, Supreeth Mysore Shivananda Murthy, Jennifer Judy Dominic Jawahar
Publikováno v:
IET Circuits, Devices & Systems. 10:94-103
The clock distribution network primarily comprises of the clock tree and the flip-flops. The resonant clocking, which drives a clock tree possesses a large potential for a sweeping power minimisation in the clock network. In addition, the clocked fli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1ed425ab044e479707a14b4bf44e7b9
https://doi.org/10.1049/iet-cds.2014.0282
https://doi.org/10.1049/iet-cds.2014.0282
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:2068-2081
The portion of clock power in system is rapidly increasing with the continuous increasing of clock frequency and clock resources. Last two decades, a great research attention has been paid to minimizing the clock power. Recently, it is shown that the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3165b478d13327605c841eb9bf59c4ad
https://doi.org/10.1109/tcad.2016.2543022
https://doi.org/10.1109/tcad.2016.2543022