Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Umesh Gajanan Nawathe"'
Autor:
King C. Yen, Aparna Ramachandran, Timothy P. Johnson, Yongning Sheng, Jason M. Hart, Daisy Jian, Rakesh Mehta, Yuefei Ge, Dawei Huang, Lance Kwong, Hoyeol Cho, Zuxu Qin, Changku Hwang, Jinuk Luke Shin, Umesh Gajanan Nawathe, Robert P. Masleid, Venkat Krishnaswamy, Georgios Konstadinidis, Hari Sathianathan, Gregory Gruber, Sebastian Turullols
Publikováno v:
ISSCC
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a65bf3aeb8482508a1512e9ba2b864
https://doi.org/10.1109/jssc.2013.2284648
https://doi.org/10.1109/jssc.2013.2284648
Autor:
King C. Yen, Amit Kumar, David J. Greenhill, Umesh Gajanan Nawathe, Mahmud Hassan, Aparna Ramachandran
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:6-20
The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Pow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d30300acb31dce6ba2b28f6781cd06c8
https://doi.org/10.1109/jssc.2007.910967
https://doi.org/10.1109/jssc.2007.910967
Autor:
Umesh Gajanan Nawathe
Publikováno v:
CMOS Processors and Memories ISBN: 9789048192151
The field of Microprocessor design came into existence in the early 1970s with the first microprocessor from Intel (the 4004). Since then, the technology and complexity of Microprocessors has increased exponentially following Moore’s Law, which imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb4ee9251e8b39b2c60b00497e8be795
https://doi.org/10.1007/978-90-481-9216-8_1
https://doi.org/10.1007/978-90-481-9216-8_1
Autor:
Umesh Gajanan Nawathe, Timothy Johnson
Publikováno v:
ISPD
This talk will provide an overview of the Niagara 2 architecture, its physical implementation, and the challenges faced with designing a 65nm SoC microprocessor. Details will also be shared with respect to Niagara 2's clocking scheme and unique desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f2a13df04a2ebb2e43f2139da321b80c
https://doi.org/10.1145/1231996.1232000
https://doi.org/10.1145/1231996.1232000