Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Ui-Hyoung Lee"'
Autor:
Ghalia Tello, Omar Y. Al-Jarrah, Paul D. Yoo, Sami Muhaidat, Yousof Al-Hammadi, Ui-Hyoung Lee
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 31:315-322
Semiconductor manufacturers aim to fabricate defect-free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93a70f5c221927322757602b97cb55f4
https://doi.org/10.1109/tsm.2018.2825482
https://doi.org/10.1109/tsm.2018.2825482
Publikováno v:
Korean Journal of Metals and Materials. 54:469-474
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cca90ccb4e4832ffe75f04b6ab90b841
https://doi.org/10.3365/kjmm.2016.54.6.469
https://doi.org/10.3365/kjmm.2016.54.6.469
Autor:
Sami Muhaidat, Fatima Adly, Mohammed Ismail, Young-Seon Jeong, Kamal Taha, Yousof Al-Hammadi, Paul D. Yoo, Ui-Hyoung Lee, Omar Alhussein
Publikováno v:
IEEE Transactions on Industrial Informatics. 11:1267-1276
Wafer defects, which are primarily defective chips on a wafer, are of the key challenges facing the semiconductor manufacturing companies, as they could increase the yield losses to hundreds of millions of dollars. Fortunately, these wafer defects le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::120f8c993d4798f72613aa8c92243342
https://doi.org/10.1109/tii.2015.2481719
https://doi.org/10.1109/tii.2015.2481719
Autor:
Hyo-Jong Lee, Sang-Hyuk Kim, Han-Kyun Shin, Chae-Min Park, Dong-Uk Kim, Pil-Ryung Cha, Ui-hyoung Lee
Publikováno v:
Korean Journal of Metals and Materials. 53:495-499
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f709319826c4990d4044a025dc93b27
https://doi.org/10.3365/kjmm.2015.53.7.495
https://doi.org/10.3365/kjmm.2015.53.7.495
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 28:145-152
Defect detection and classification in semiconductor wafers has received an increasing attention from both industry and academia alike. Wafer defects are a serious problem that could cause massive losses to the companies’ yield. The defects occur a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2d85b08d87d90b1c1e063686fa6ddf4
https://doi.org/10.1109/tsm.2015.2405252
https://doi.org/10.1109/tsm.2015.2405252
Autor:
Cheng Xu, Wenqi Zhang, Chongshen Song, Zhongcai Niu, Ui-Hyoung Lee, Jaihyung Won, Jong-yong Bae, Xiangmeng Jing
Publikováno v:
ECS Transactions. 66:183-191
Stacking of ICs using three-dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnection latency, and power dissipation while enhancing performance. Through silicon vias (TSVs) are regarded as a key enabling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::85fadbce428c5418d635ff5be30916f0
https://doi.org/10.1149/06604.0183ecst
https://doi.org/10.1149/06604.0183ecst
Autor:
Youngseok Song, Ui-Hyoung Lee, Hyoung Jin Jeon, Seok-Hwan Huh, Sung Keun Lee, Hyo Jong Lee, Hyun-Soo Chu
Publikováno v:
Korean Journal of Metals and Materials. 52:943-948
Copper electrodeposits annealed at 80 °C were investigated by electrical resistance measurement, X-ray diffraction and electron backscattered diffraction analyses. The decrease of electrical resistivity had a linear relationship with the re-crystall
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37055aebae378cf66ea95be07f97b470
https://doi.org/10.3365/kjmm.2014.52.11.943
https://doi.org/10.3365/kjmm.2014.52.11.943
Autor:
Suncheul Kim, Jong-yong Bae, Miseok Park, Yong Il Kwon, Dong-Hoon Han, Ui-Hyoung Lee, Yoonbon Koo
Publikováno v:
ECS Meeting Abstracts. :1179-1179
Recent developments in CMOS (Complementary Metal-Oxide-Semiconductor) technology have heightened the need for high-quality interface between mold and metal line, in order to decrease the RC delay in CMOS circuit. This technical trend indicates that t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b65116c5dea44421d221a8e7a23d6a03
https://doi.org/10.1149/ma2019-01/23/1179
https://doi.org/10.1149/ma2019-01/23/1179
Publikováno v:
2015 16th International Conference on Electronic Packaging Technology (ICEPT).
Through silicon via (TSV) based 2.5D and 3D integration technology is regarded as the most promising enabling technology for next generation system integration. One of the concerns associated with TSV is the reliability issue of the TSV based devices
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6206616c2e5b1ce485536b4ab9e09b8
https://doi.org/10.1109/icept.2015.7236655
https://doi.org/10.1109/icept.2015.7236655
Publikováno v:
2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.
Cu pumping is a potential reliability issue for through silicon via (TSV) based 2.5D and 3D integration, due to the CTE mismatch between silicon and copper. In this paper, we report the reliability assessment of Cu pumping treated at different anneal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad583bd783affc56814b542d09de6446
https://doi.org/10.1109/ipfa.2015.7224329
https://doi.org/10.1109/ipfa.2015.7224329