Hardware cost evaluation of the posit number system

Autor: Forget, Luc, Uguen, Yohann, De Dinechin, Florent

Publikováno v: Compas'2019-Conférence d'informatique en Parallélisme, Architecture et Système
Compas'2019-Conférence d'informatique en Parallélisme, Architecture et Système, Jun 2019, Anglet, France. pp.1-7

National audience; The posit number system is proposed as a replacement of IEEE floats. It encodes floating-point values with tapered precision: numbers whose exponent is close to 0 have more precision than IEEE floats, while numbers with high-magnit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::9273f9f2b119aa706b96e2d47db75520
https://hal.inria.fr/hal-02131982

High-level synthesis and arithmetic optimizations

Autor: Uguen, Yohann

Publikováno v: Computer Arithmetic. INSA Lyon, 2019. English

High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming.However, due to their relatively young nature, they still lack many arithmetic optimizations.This thesis proposes safe arithmetic optimizations that should alway

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od_______212::4e2934895709d4d0564c8f2484b339e9
https://hal.archives-ouvertes.fr/tel-02420901/file/manuscript.pdf

Design-space exploration for the Kulisch accumulator

Autor: Uguen, Yohann, de Dinechin, Florent

Floating-point sums and dot products accumulate rounding errors that may render the result very inaccurate. To address this, Kulisch proposed to use an internal accumulator large enough to cover the full exponent range of floating-point. With it, sum

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1a547d2f37356bf68699f6198911066a
https://hal.archives-ouvertes.fr/hal-01488916v2

High-Level Synthesis Using Application-Specific Arithmetic: A Case Study

Autor: Uguen, Yohann, de Dinechin, Florent, Derrien, Steven

On the one hand, a strength of FPGAs is their ability to perform non-standard computations not supported by classical microprocessors. Many libraries of highly customizable application-specific IPs have been developed to exploit this strength. On the

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::0605c394914d0ea19f26d4bf057537da
https://hal.science/hal-01502644

Evaluating the hardware cost of the posit number system

Autor: Luc Forget, Florent de Dinechin, Yohann Uguen

Publikováno v: FPL 2019-29th International Conference on Field-Programmable Logic and Applications (FPL)
FPL 2019-29th International Conference on Field-Programmable Logic and Applications (FPL), Sep 2019, Barcelona, Spain. pp.106-113
FPL

International audience; The posit number system is proposed as a replacement of IEEE floating-point numbers. It is a floating-point system that trades exponent bits for significand bits, depending on the magnitude of the numbers. Thus, it provides mo

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::abd504666a3cdb74ea4dbca44d127131
https://inria.hal.science/hal-02130912v4/file/hal_marto_final.pdf