Výsledky vyhledávání - "Uday Mallappa"

DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs

Autor: Chung-Kuan Cheng, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa

Publikováno v: ACM Transactions on Design Automation of Electronic Systems. 28:1-31

The objective of a leakage recovery step is to make use of positive slack and reduce power by performing appropriate standard-cell swaps such as threshold-voltage ( V th ) or channel-length reassignments. The resulting engineering change order netlis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::86c1ad72444e595ed0a24fa9c9286bec
https://doi.org/10.1145/3577019

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GRA-LPO

Autor: Uday Mallappa, Chung-Kuan Cheng

Publikováno v: ASP-DAC

Static power consumption is a critical challenge for IC designs, particularly for mobile and IoT applications. A final post-layout step in modern design flows involves a leakage recovery step that is embedded in signoff static timing analysis tools.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::78b0eb1b5640f08ec4a20835fd2e279c
https://doi.org/10.1145/3394885.3431574

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Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques

Autor: Bangqi Xu, Sachin S. Sapatnekar, Min-Soo Kim, Uday Mallappa, Vidya A. Chhabria, Andrew B. Kahng

Publikováno v: ASP-DAC

Designing an optimal power delivery network (PDN) is a time-intensive task that involves many iterations. This paper proposes a methodology that employs a library of predesigned, stitchable templates, and uses machine learning (ML) to rapidly build a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0008ba35af970c70be0d3ffc5635e676
https://doi.org/10.1109/asp-dac47756.2020.9045303

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Toward an Open-Source Digital Flow

Publikováno v: DAC

We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::87dc3ca80acf5db3c63a7cf038340058
https://doi.org/10.1145/3316781.3326334

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'Unobserved Corner' Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design

Autor: Lawrence K. Saul, Andrew B. Kahng, Uday Mallappa, Shangyuan Tong

Publikováno v: DATE

With diminishing margins for leading-edge products in advanced technology nodes, design closure and accuracy of timing analysis have emerged as serious concerns. A significant portion of design turnaround time is spent on timing analysis at combinati

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5ae9979d0994d1a08f49e78094d73b68
https://doi.org/10.23919/date.2019.8715102

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