Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Tze Chiang Tin"'
Publikováno v:
IEEE Access, Vol 10, Pp 81960-81973 (2022)
Physical metrology inspections are crucial in semiconductor fabrication to ensure that wafers are fabricated within the production specification limits and to prevent faulty wafers from being shipped and installed in customer devices. However, it is
Externí odkaz:
https://doaj.org/article/4bcfc5a60a9c4032ad6b4e63e9245c0d
Autor:
Tze Chiang Tin, Saw Chin Tan, Hing Yong, Jimmy Ook Hyun Kim, Eric Ken Yong Teo, Ching Kwang Lee, Peter Than, Angela Pei San Tan, Siew Chee Phang
Publikováno v:
IEEE Access, Vol 9, Pp 65418-65439 (2021)
Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and imprac
Externí odkaz:
https://doaj.org/article/383f69dab4b14d2a8853e07d64626e36
Autor:
Tze Chiang Tin, Saw Chin Tan, Hing Yong, Jimmy Ook Hyun Kim, Eric Ken Yong Teo, Joanne Ching Yee Wong, Ching Kwang Lee, Peter Than, Angela Pei San Tan, Siew Chee Phang
Publikováno v:
IEEE Access, Vol 9, Pp 114255-114266 (2021)
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to es
Externí odkaz:
https://doaj.org/article/1af0ef8f16bd4ef98eb015984544eed7
Autor:
Eric Ken Yong Teo, Siew Chee Phang, Hing Yong, Saw Chin Tan, Ching Kwang Lee, Tze Chiang Tin, Peter Than, Jimmy Ook Hyun Kim, Angela Pei San Tan
Publikováno v:
IEEE Access, Vol 9, Pp 65418-65439 (2021)
Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and imprac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c6f82358c9fbfe8313ffbb276d4e3fff
https://doi.org/10.1109/access.2021.3076193
https://doi.org/10.1109/access.2021.3076193
Autor:
Jimmy Ook Hyun Kim, Ching Kwang Lee, Tze Chiang Tin, Hing Yong, Joanne Ching Yee Wong, Peter Than, Saw Chin Tan, Angela Pei San Tan, Siew Chee Phang, Eric Ken Yong Teo
Publikováno v:
IEEE Access, Vol 9, Pp 114255-114266 (2021)
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to es
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c07088dc03d1bbb4694fe965ea5970ee
https://doi.org/10.1109/access.2021.3103235
https://doi.org/10.1109/access.2021.3103235
Publikováno v:
Computational Intelligence and Neuroscience
Computational Intelligence and Neuroscience, Vol 2019 (2019)
Computational Intelligence and Neuroscience, Vol 2019 (2019)
Preventive maintenance activities require a tool to be offline for long hour in order to perform the prescribed maintenance activities. Although preventive maintenance is crucial to ensure operational reliability and efficiency of the tool, long hour
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1f740012fa0cfbdcd5a24e09c76c3501
http://europepmc.org/articles/PMC6334351
http://europepmc.org/articles/PMC6334351