Výsledky vyhledávání - "Tung Hsing Lee"

A Novel Method to Improve Laser Anneal Worsened Negative Bias Temperature Instability in 40-nm CMOS Technology

Autor: Tung-Hsing Lee, Ming-Shing Chen, Cheng-I Lin, Yen-Ting Chiang, Feng-Renn Juang, Judy Ning, Yean-Kuen Fang, Sam Chou

Publikováno v: IEEE Transactions on Electron Devices. 58:901-905

From the measured data, the impact of the rapid thermal process (RTP) and laser spike anneal (LSA) sequence on negative bias temperature instability (NBTI) and current gain was investigated on 40-nm complementary metal-oxide semiconductor technology.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::31fb8e2d5384495260abdd1f220f9c55
https://doi.org/10.1109/ted.2010.2102358

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Effect of Finger Pitch on the Driving Ability of a 40-nm MOSFET With Contact Etch Stop Layer Strain in Multifinger Gated Structure

Autor: Chii-Wen Chen, Cheng-I Lin, Ming-Shing Chen, Tung-Hsing Lee, Chih-Yu Tseng, Sam Chou, Yen-Ting Chiang, Feng-Renn Juang, Yean-Kuen Fang

Publikováno v: IEEE Transactions on Electron Devices. 57:1355-1361

Effects of the poly gate finger pitch on, hot-carrier-nduced reliability degradation, and radio frequency characteristics of the 40-nm n-channel metal-oxide-semiconductor field-effect transistors with contact-etch-stop-layer (CESL) strain and multifi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bcaf8cff44f0fd456adda703392ea1ed
https://doi.org/10.1109/ted.2010.2046699

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Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide

Autor: Yen-Ting Chiang, Ming-Shing Chen, Joe Ko, Yau Kae Sheu, Wen Yi Liao, Chien-Ting Lin, Yean-Kuen Fang, Tung-Hsing Lee, Tsong Lin Shen

Publikováno v: Japanese Journal of Applied Physics. 47:2624-2627

Negative bias temperature instability (NBTI) in a dual-gate-oxide complementary metal–oxide–semiconductor (CMOS) process induces threshold voltage (Vt) shift and has become a crucial challenge in designing advanced analog or mixed-signal circuits

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::44c2f6c7f0afe22723e74cb962c6bf68
https://doi.org/10.1143/jjap.47.2624

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Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches

Autor: Wen-Kuan Yeh, Hui Chen Chang, Liang Wei Chen, Cheng Tzung Tsai, M. Ma, Chien-Ting Lin, Che Hua Hsu, Yean-Kuen Fang, Ming Hing Chen, Tung Hsing Lee

Publikováno v: Japanese Journal of Applied Physics. 45:3049-3052

The interactions of shallow trench isolation (STI) stress and various mobility enhancement approaches in silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) have been systematically studied. Strong interactions between STI stres

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ac6495e660d5964a411ac4719b8f20c4
https://doi.org/10.1143/jjap.45.3049

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PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

Publikováno v: IEEE Electron Device Letters. 28:815-817

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performan

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c39cea1503be3ef09027c508ef5d6313
https://doi.org/10.1109/led.2007.902613

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A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance

Autor: Chien-Ting Lin, Tung-Hsing Lee, Wen-Kuan Yeh, M. Ma, Liang-Wei Chen, Ming-Shing Chen, Li-Wei Cheng, Chieh-Ming Lai, Che-Hua Hsu, Yean-Kuen Fang

Publikováno v: IEEE Electron Device Letters. 28:111-113

A novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::04b455523ebe40cce18b00cd7348ca06
https://doi.org/10.1109/led.2006.889633

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Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI

Autor: Che-Hua Hsu, Chien-Ting Lin, Wen-Kuan Yeh, M. Ma, Tung-Hsing Lee, Yean-Kuen Fang, Liang-Wei Chen, Li-Wei Cheng, Ming-Shing Chen

Publikováno v: IEEE Electron Device Letters. 27:963-965

In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::97a5fe9bfa9dfcf165e030559ee17cd8
https://doi.org/10.1109/led.2006.886715

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Capping layer induced degradations in nano MOSFETs with scaled IL

Autor: Li-Wei Cheng, Tung-Hsing Lee, Che-Hua Hsu, Chien-Ming Lai, Feng-Renn Juang, Yi-Wen Chen, S-M Chen, Chia-Wei Hsu, Yean-Kuen Fang

Publikováno v: The 4th IEEE International NanoElectronics Conference.

EOT scale down is a critical issue in LaO/AlO capped Hf-based devices, because it will result in serious V FB roll-off. The incorporation of capping layer induces more traps in the gate stack. These traps are oxygen vacancy related defects and are se

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e016bb841fa759c150f25f92d23563df
https://doi.org/10.1109/inec.2011.5991785

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