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Autor:
C. W. Yeh, Yu Zhu, Asit Kumar Ray, Mark D. Drapa, Chung H. Lam, Junka Okazawa, Scott C. Lewis, Sangbum Kim, Wanki Kim, Matt BrightSky, Tu-Shun Chen, Tony Perri, Robert L. Bruce, Jack Morrish, Huai-Yu Cheng, Chia-Jung Chen, Kohji Hosokawa, Wei-Chih Chien, Thomas M. Maffitt, Richard C. Jordan, Yutaka Nakamura, Hsiang-Lan Lung, Yung-Han Ho, H. Y. Ho, Christopher P. Miller, Jerry Heath
Publikováno v:
2016 IEEE 8th International Memory Workshop (IMW).
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications .