Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Tsuyoshi Ebuchi"'
Publikováno v:
IEICE Electronics Express. 15:20171151-20171151
Autor:
Yoshihide Komatsu, Takashi Hirata, Takashi Morie, Shiro Dosho, Kazuaki Sogawa, Tsuyoshi Ebuchi, Takefumi Yoshikawa, Yuji Yamada, Kouji Okamoto, Yukio Arima, T. Okamoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:763-774
A process-independent adaptive bandwidth spread-spectrum clock generator (SSCG) with digitally controlled self-calibration techniques is proposed. By adaptively calibrating the VCO gain (Kv) and charge-pump (CP) current over C (ICP/C), the SSCG can r
Autor:
Tsuyoshi Ebuchi, Takashi Hirata, Yukio Arima, Takefumi Yoshikawa, Toru Iwata, Hiroyuki Yamauchi
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16:1187-1198
This paper describes an area-effective 1.5-Gb/s transceiver core with spread spectrum clocking (SSC) capability that is suitable for integration into large system-on-chips (SoCs) for consumer electronics applications such as audio and video stream da
Publikováno v:
IEICE Transactions on Electronics. :1444-1452
A transceiver macro for high-speed data transmission via cable in vehicles is proposed. The transceiver uses ac coupling and bidirectional interface topology for protecting LSIs against unexpected short of cable and harness/chassis and has a spread-s
Autor:
Tomoko Chiba, Masatomo Miura, Shiro Dosho, Yoshihide Komatsu, Takefumi Yoshikawa, Tsuyoshi Ebuchi, Toru Iwata
Publikováno v:
2010 Symposium on VLSI Circuits.
A transceiver with adaptive power control using a process and frequency monitor (PFM) is proposed. The PFM employs gain calibration with a replica voltage-controlled oscillator (VCO) and operates in the background. A five-bit digital code detected by
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long ca
Autor:
Yoshihide Komatsu, T. Yoshida, Yukio Arima, H. Kimura, T. Yoshikawk, Tsuyoshi Ebuchi, Hiroyuki Yamauchi, K. Nishimura, Toru Iwata
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A physical layer LSI has one DS-port and two /spl beta/ports in accordance with IEEE1394-2000 and P1394b Draft 1.01 respectively. The 0.25 /spl mu/m CMOS LSI realizes 800 Mb/s and 1.2 km peer-to-peer IEEE1394 networking through /spl beta/port. Each /
Autor:
Takefumi Yoshikawa, Tomohiro Tsuchiya, Toru Iwata, Watanabe Seiji, Keijiro Umehara, Tsuyoshi Ebuchi, Tomoko Chiba, Taku Toshikawa, Yutaka Terada
Publikováno v:
IEICE Electronics Express. 11:20140949-20140949
Publikováno v:
IEICE Transactions on Electronics. :1288-1289
A Spread Spectrum Clock Generator (SSCG) using Digital Tracking scheme (DT-SSCG) is described. Using digital tracking control outside a PLL, DT-SSCG can realize stable modulation characteristic independent of the PLL constants. Moreover, DT-SSCG can