Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Tsuneo Inaba"'
Autor:
Ki-Seon Park, Tsuneo Inaba, Hiromi Noro, Jonghoon Oh, Sung-Woong Chung, Akihito Yamamoto, Hyeongon Kim, Hisato Oyamatsu, Kazumasa Sunouchi, Jinwon Park, Yutaka Shirai, Seoung-Ju Chung, Dong-Keun Kim, Kenji Tsuchida, Ji-Hyae Bae, Hyunin Moon, Kwang-Myoung Rho
Publikováno v:
ISSCC
Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel jun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5e7dd5fe478f795d6d980cb7a53276
https://doi.org/10.1109/isscc.2017.7870428
https://doi.org/10.1109/isscc.2017.7870428
Publikováno v:
Journal of Crystal Growth. 138:403-407
A novel nitrogen exciter for p-type doping of ZnSe has been developed. It is of a sample structure, easy to handle and to maintain, of a high reliability, and inexpensive. Emission spectra from excited nitrogen and doping efficiency are studied for d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd46cd71678a0b9c374da8378925a380
https://doi.org/10.1016/0022-0248(94)90841-9
https://doi.org/10.1016/0022-0248(94)90841-9
Autor:
Katsuyuki Fujita, Yohji Watanabe, Yoshihiro Ueda, Tadashi Kai, Kuniaki Sugiura, Takafumi Shimizu, Masayoshi Iwayama, Yoshiaki Asao, Minoru Amano, Sumio Ikegawa, Hiroaki Yoda, Tatsuya Kishi, Tsuneo Inaba, Takeshi Kajiyama, Naoharu Shimomura, Kenji Tsuchida
Publikováno v:
ISSCC
In order to realize a sub-Giga bit scale NVRAM, the novel MRAM based on the spin-transfer-torque (STT) switching has been intensively investigated due to its excellent scalability compared with a conventional magnetic field induce switching MRAM [1].
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1970847db86c96153417ee5abe20f46
https://doi.org/10.1109/isscc.2010.5433948
https://doi.org/10.1109/isscc.2010.5433948
Autor:
Ryousuke Takizawa, Shuichi Tahara, Keiji Hosotani, T. Sugibayashi, Takeshi Kajiyama, Tsuneo Inaba, Masahiko Nakayama, Yoshihisa Iwata, K. Tsuchida, Yuui Shimizu, Yoshiaki Asao, Yuji Ueda, Sumio Ikegawa, Hiroaki Yoda, Tadashi Kai
Publikováno v:
ISSCC
A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is rais
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4faa8e6788b6787ff00bb7cdbf5e3adb
https://doi.org/10.1109/isscc.2006.1696080
https://doi.org/10.1109/isscc.2006.1696080
Publikováno v:
CICC
A novel resistance ratio read (R/sup 3/) architecture for a magnetoresistive random access memory (MRAM), which realizes a burst read operation and higher fluctuation immunity of MTJ resistance, is proposed. In this architecture, a memory cell consis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e3c1a69e17e6ef917ae0637de797df7
https://doi.org/10.1109/cicc.2003.1249427
https://doi.org/10.1109/cicc.2003.1249427
Autor:
Tsuneo Inaba, Katsuaki Isobe, F. Kouno, Shinichiro Shiratake, H. Kuyama, M. Wada, Kenji Tsuchida, Hironobu Akita, H. Toda
Publikováno v:
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9f36724c09e6cdd8813adcb54f0307c
https://doi.org/10.1109/vlsic.1999.797260
https://doi.org/10.1109/vlsic.1999.797260
Autor:
Shigeyoshi Watanabe, Yukihito Oowaki, Daisaburo Takashima, Kenji Tsuchida, Tsuneo Inaba, Shinichiro Shiratake, J. Matsunaga, Kazuya Ohuchi, M. Ohta, Hiroaki Nakano
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::668cdeb6bb48525eb16ed9444ac98cf8
https://doi.org/10.1109/vlsic.1996.507766
https://doi.org/10.1109/vlsic.1996.507766
Autor:
Tsuneo Inaba, Shigeyoshi Watanabe, Kazuya Ohuchi, Yukihito Oowaki, T. Ozaki, Daisaburo Takashima
Publikováno v:
Digest of Technical Papers., Symposium on VLSI Circuits..
We have proposed a new 1/4 Vcc bit-line swing architecture and related sense amplifier for 1 V 4 Gb DRAM and beyond. These schemes reduce power dissipation to 40% without degradation of the read-out signal and also improve device reliability.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be5ca51707834ae63cb45cc282747bd6
https://doi.org/10.1109/vlsic.1995.520704
https://doi.org/10.1109/vlsic.1995.520704
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