Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Tsukasa Tokutomi"'
Publikováno v:
Solid-State Electronics. 111:129-140
To improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012, 2013), which is effective for long retention tim
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:844-853
This paper proposes design methodology for highly reliable, high performance ReRAM and 3-bit/cell multi-level cell (MLC) NAND flash solid-state storage. Six techniques, calibrated RRef (CR), flexible RRef (FR), adaptive asymmetric coding (AAC), verif
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:771-780
This paper proposes highly reliable coding methods for applications in two extreme conditions. n-out-of-8 level cell (nLC) is proposed for archival applications which require significantly long data-retention time with small write/erase cycle. On the
Publikováno v:
VLSI Circuits
Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cy
Autor:
Tsukasa Tokutomi, Ken Takeuchi
Publikováno v:
2016 IEEE 8th International Memory Workshop (IMW).
Highly reliable LDPC ECC is introduced to improve the reliability of solid-state drives (SSDs). Although conventional AEP-LDPC ECC [3] is 12x highly reliable than BCH ECC, its error-correction capability is degraded due to the burst-errors and inaccu
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
Read-disturb Modeled LDPC (RDM-LDPC) ECC is proposed. Conventional Advanced Error-Prediction LDPC (AEP-LDPC) [1] corrects data-retention errors of data-storage-purpose SSDs storing photos, movies, etc. but cannot correct read-disturb errors. For read
Autor:
Tsukasa Tokutomi, Masafumi Doi, Ken Takeuchi, Shogo Hachiya, Shuhei Tanakamaru, Atsuro Kobayashi
Publikováno v:
ISSCC
An enterprise-grade SSD with TLC (3b/cell) NAND Flash is presented with three techniques that achieve high speed and high reliability. Quick low-density parity-check (LDPC) reduces the read latency of 1Xnm TLC NAND Flash SSD by 83%. Dynamic l/ TH opt
Publikováno v:
VLSIC
Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can
Publikováno v:
2014 IEEE 6th International Memory Workshop (IMW).
Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash's capacity, bits/cell have been doubled and tripled, which causes
Publikováno v:
ISSCC
A hybrid storage architecture of ReRAM and TLC (3b/cell) NAND Flash with RAID-5/6 is developed to meet cloud data-center requirements of reliability, speed and capacity. The storage controller enhances reliability and performance through five techniq