Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Tsukasa Shirotori"'
Autor:
Man Kit Tang, M. Matsui, Takayasu Sakurai, T. Kobayashi, Yasuo Unekawa, Yukihiro Fujimoto, Kazuhiro Sawada, Kazutaka Nogami, Tsukasa Shirotori, T. Shimazawa, T. Nakao, W.A. Huffman
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:403-410
A 4-way set associative TagRAM with 1.189-Mb capacity has been developed which can handle a secondary cache system of up to 16 Mbytes. A 9-ns cycle operation and clock to D/sub out/ of 4.7 ns are achieved by use of circuit techniques such as a pipeli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::407b875f79dac6a7f4c6568bff8665ab
https://doi.org/10.1109/4.280688
https://doi.org/10.1109/4.280688
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:523-527
Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aaeb715aae3ee5c06551aa5f02738d0d
https://doi.org/10.1109/4.210039
https://doi.org/10.1109/4.210039
Autor:
T. Kobayashi, Y. Biwaki, M. Kobayashi, Koichi Kobayashi, Kazutaka Nogami, Kazuhiro Sawada, H. Nohara, Tsukasa Shirotori, Yukihiro Fujimoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1586-1592
A 64-kbyte snoopy cache memory was developed. The modified double word-line architecture with word-line buffers resulted in a large-size memory and a time-multiplex snoop operation by the pseudo-two-port method with a single-port cell. The flexible e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13aa36d24c89d99fda4e9bbc04564384
https://doi.org/10.1109/4.98976
https://doi.org/10.1109/4.98976
Autor:
Tsukasa Shirotori, Takayasu Sakurai, Sumio Tanaka, Tetsuya Iizuka, Yuichi Miyazawa, Toshinari Takayanagi, Kazutaka Nogami, Kazuhiro Sawada, Masanori Uchida, K. Katoh, Yoichi Hiruta, Kenji Sakaue, Y. Itoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:100-108
A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76417ccd9d3d6a0fdfee45e214790a21
https://doi.org/10.1109/4.50291
https://doi.org/10.1109/4.50291
Autor:
Tsukasa Shirotori, H. Nohara, Y. Biwaki, Koichi Kobayashi, Kazuhiro Sawada, M. Kobayashi, Kazutaka Nogami, T. Kobayashi, Yukihiro Fujimoto
Publikováno v:
1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::117e0e7de1721f3e9cc19ec80d3d5daa
https://doi.org/10.1109/isscc.1991.689154
https://doi.org/10.1109/isscc.1991.689154
Publikováno v:
Journal of the Ceramic Society of Japan. 97:812-817
The effect of a second phase (ZrO2 particles) on the thermal shock resistance of MgO was investigated. MgO doped with 1mol% LiF and MgO dispersed with 10mol% ZrO2 (t-ZrO2 or c-ZrO2) were fabricated by sintering. Sintered specimens were heated to vari
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::293a210f057b6a581739d5824b9b1415
https://doi.org/10.2109/jcersj.97.812
https://doi.org/10.2109/jcersj.97.812
Autor:
Yoshiki Hayakashi, J. Matsunaga, Tetsuya Iizuka, Kazuhiro Sawada, Hiromichi Fuji, T. Maeda, Akio Miyoshi, Koichi Kobayashi, Tomoyuki Ando, Kazuyuki Sato, Takayasu Sakurai, Kazutaka Nogami, Toshinari Takayanagi, Tsukasa Shirotori, K. Maeguchi
Publikováno v:
IEEE Journal of Solid-State Circuits. 24:881-888
The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory siz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::245208606c66ea7d93844467ef2dce10
https://doi.org/10.1109/4.34065
https://doi.org/10.1109/4.34065
Autor:
T. Asami, Tetsuya Iizuka, M. Kakuma, Kazuhito Narita, Kazutaka Nogami, J. Matsunaga, M. Kinugawa, Tsukasa Shirotori, Kazuyuki Sato, Kazuhiro Sawada, Akira Higuchi, Takayasu Sakurai, M. Isobe, Morita Shigeru
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:12-19
A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is gr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82c0e946bf51a223ad44fc60561796af
https://doi.org/10.1109/4.250
https://doi.org/10.1109/4.250
Autor:
Tsukasa Shirotori, K. Maeguchi, Takayasu Sakurai, Yoshiki Hayakashi, Takeo Maeda, Akio Miyoshi, Hiromichi Fuji, Kazuhiro Sawada, Toshinari Takayanagi, Kazuyuki Sato, Tomoyuki Ando, Kiyoshi Kobayashi, Kazutaka Nogami, J. Matsunaga, Tetsuya Iizuka
Publikováno v:
ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.
The architectural aspects of a newly deveoped integrated cache memory is described in this paper, which includes 32Kbyte DATA memory with a typical ADDRESS to HIT delay, the largest memory size and fastest speed ever reported as an integrated cache m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::892dcc05409356e3213c24466787375d
https://doi.org/10.1109/esscirc.1988.5468419
https://doi.org/10.1109/esscirc.1988.5468419
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