Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Trey Greer"'
Autor:
Michael Stengel, Josef Spjut, Ben Boudaoud, Trey Greer, Rachel Albert, Kaan Akşit, Jonghyun Kim, David Luebke
Publikováno v:
IEEE Transactions on Visualization and Computer Graphics. 26:2126-2134
Emergent in the field of head mounted display design is a desire to leverage the limitations of the human visual system to reduce the computation, communication, and display workload in power and form-factor constrained systems. Fundamental to this r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f2590eba0e65756691a6807dc1d16e69
https://doi.org/10.1109/tvcg.2020.2973053
https://doi.org/10.1109/tvcg.2020.2973053
Autor:
Morgan McGuire, Michael Stengel, David Luebke, Ben Boudaoud, Jonghyun Kim, Rachel Albert, Zander Majercik, Josef Spjut, Ward Lopes, Kaan Akşit, Youngmo Jeong, Joohwan Kim, Trey Greer, Peter Shirley
Publikováno v:
ACM Transactions on Graphics. 38:1-15
We present a near-eye augmented reality display with resolution and focal depth dynamically driven by gaze tracking. The display combines a traveling microdisplay relayed off a concave half-mirror magnifier for the high-resolution foveal region, with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e48d6423c8dfba7863542f88a1e41d93
https://doi.org/10.1145/3306346.3322987
https://doi.org/10.1145/3306346.3322987
Autor:
Youngmo Jeong, Michael Stengel, Morgan McGuire, Ben Boudaoud, Rachel Albert, Jonghyun Kim, Ward Lopes, Peter Shirley, Jui-Yi Wu, Zander Majercik, Kaan Akşit, Josef Spjut, Trey Greer, David Luebke
Publikováno v:
SIGGRAPH Emerging Technologies
An increasingly important part of usuable near-eye displays to allow use by users who use vision correction such as that provided by glasses and contact lenses. Recent research indicates that over 20% of world population is myopic, and this percentag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::654cfd4ea43a86518335dcf9529d4b2b
https://doi.org/10.1145/3305367.3327978
https://doi.org/10.1145/3305367.3327978
Autor:
Nhat Nguyen, John Eyles, Michael Bucher, Andrew M. Fuller, John Wilson, Robert E. Palmer, John W. Poulton, Trey Greer, Simon Li, Yohan Frans, Marko Aleksic, Brian S. Leibowitz
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:889-898
This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d085e3b7d821f760c88e3623b8ef065b
https://doi.org/10.1109/jssc.2010.2040230
https://doi.org/10.1109/jssc.2010.2040230
Autor:
R. Rathi, William J. Dally, R. Senthinathan, Hiok-Tiaq Ng, Trey Greer, M.-J.E. Lee, J. Edmondson, John W. Poulton, J. Tran, A. Nguyen, Ramin Farjad-Rad
Publikováno v:
CICC
A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking ap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::601c792276566dd0b8fd81c870c55a98
https://doi.org/10.1109/jssc.2004.831457
https://doi.org/10.1109/jssc.2004.831457
Autor:
Hiok-Tiaq Ng, Trey Greer, William J. Dally, Ramin Farjad-Rad, John W. Poulton, J. Edmondson, R. Senthinathan, R. Rathi, M.-J.E. Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:2101-2110
A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d265a5bd916c1c93eef2c159e579a74d
https://doi.org/10.1109/jssc.2003.818576
https://doi.org/10.1109/jssc.2003.818576
Autor:
Hiok-Tiaq Ng, Trey Greer, M.-J.E. Lee, R. Senthinathan, Ramin Farjad-Rad, William J. Dally, John W. Poulton
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:614-621
This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3282441bc608332a8ef0a17accb1c986
https://doi.org/10.1109/jssc.2003.809519
https://doi.org/10.1109/jssc.2003.809519
Autor:
Metha Jeeradit, Vladimir Stojanovic, William F. Stonecypher, Trey Greer, B.W. Gariepp, Nhat Nguyen, Fred Heaton, Barry Daly, Hae-Chang Lee, Simon Li, Yohan Frans, B.S. Leibowitz, Jared L. Zerbe, Ramin Farjad-Rad, A. Bansal, J. Kizer, Carl W. Werner, Anh Tuan Ho, Fred F. Chen
Publikováno v:
ISSCC
A 7.5Gb/s receiver has a 3-level DFE architecture to satisfy feedback timing requirements for 10 post-cursor taps. The receiver includes a second-order CDR with partial-response transition data filtering as well as a spectrally gated adaptation engin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28a7168b03a2fafe32471a1069448d1e
https://doi.org/10.1109/isscc.2007.373377
https://doi.org/10.1109/isscc.2007.373377
Autor:
F. Quan, John W. Poulton, R. Palmer, Trey Greer, Mark Horowitz, F. Zarkeshvari, M. Kellam, William J. Dally, John Eyles, Andrew M. Fuller
Publikováno v:
ISSCC
A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c12e4e8c3980efff0c3bb48001b213c
https://doi.org/10.1109/isscc.2007.373483
https://doi.org/10.1109/isscc.2007.373483
Autor:
Steven Molnar, Trey Greer, John W. Poulton, Nick England, John Eyles, Anselmo Lastra, Lee Westover
Publikováno v:
Workshop on Graphics Hardware
PlxelFlow is an architecture for high-speed, highly realistic image generation, based on the techniques of object-parallelism and image composition, Its initial architecture was described in [MOLN92]. After development by the original team of researc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad5d9430205335c96e6f02d4a21c1ec4
https://doi.org/10.1145/258694.258714
https://doi.org/10.1145/258694.258714