60 nm gate length dual-Vt CMOS for high performance applications.

Autor: Mehrotra, M., Wu, J., Jain, A., Laaksonen, T., Kim, K., Bather, W., Koshy, R., Chen, J., Jacobs, J., Ukraintsev, V., Olsen, L., DeLoach, J., Mehigan, J., Agarwal, R., Walsh, S., Sekel, D., Tsung, L., Vaidyanathan, M., Trentman, B., Liu, K.

Publikováno v: 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303); 2002, p124-125, 2p