Zobrazeno 1 - 10
of 56
pro vyhledávání: '"Toyoji Yamamoto"'
Autor:
Toyoji Yamamoto
Publikováno v:
2019 Symposium on VLSI Technology.
Superconducting parametric amplifier, originally developed more than half a century ago, gained renewed interests in some experiments of superconducting quantum electronics about a decade ago, and now has become an indispensable tool in the field of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fbcb89044977c280bcbfc28d27cecc0
https://doi.org/10.23919/vlsit.2019.8776576
https://doi.org/10.23919/vlsit.2019.8776576
Autor:
Osamu Kiso, Naoharu Sugiyama, Kunihiro Suzuki, Keiji Ikeda, Masatomi Harada, Yoshimi Yamashita, Toyoji Yamamoto, Noriyuki Taoka, Shinichi Takagi
Publikováno v:
ECS Transactions. 13:275-285
We have fabricated NiGe/Ge diodes and Ge pMISFETs with the NiGe S/D, and studied the electrical characteristics in detail. The NiGe/n-Ge Schottcky S/D is shown to be suitable for Ge pMISFETs. The high performance Ge pMISFETs with sub-100nm gate lengt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fd3b985cce4879204cec6b19bf23d00
https://doi.org/10.1149/1.2911508
https://doi.org/10.1149/1.2911508
Autor:
Tohru Mogami, M. Narihiro, T. Ikezawa, T. Ezaki, N. Ikezawa, Toshitsugu Sakamoto, Masami Hane, H. Wakabayashi, H. Kawaura, Toyoji Yamamoto, Nobuyuki Ikarashi, Yukinori Ochiai, Kiyoshi Takeuchi
Publikováno v:
IEEE Transactions on Electron Devices. 53:1961-1970
Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b707da6ba8e44757c709e7ed1b35d01
https://doi.org/10.1109/ted.2006.880169
https://doi.org/10.1109/ted.2006.880169
Autor:
Haruhiko Ono, Toru Tatsumi, Tohru Mogami, Koji Watanabe, Toyoji Yamamoto, Mitsuhiro Togo, Nobuyuki Ikarashi
Publikováno v:
IEEE Transactions on Electron Devices. 49:1903-1909
We have developed a low-leakage and highly reliable 1.5-nm SiON gate-dielectric by using radical oxygen and nitrogen. In this development, we introduce a new method for determining an ultrathin SiON gate-dielectric thickness based on the threshold vo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e466c6e3a805107e2c8d7d1f5010c27
https://doi.org/10.1109/ted.2002.804695
https://doi.org/10.1109/ted.2002.804695
Autor:
Mitsuhiro Togo, Shigeru Kimura, Tohru Mogami, Toru Tatsumi, M. Terai, Toyoji Yamamoto, Koji Watanabe
Publikováno v:
IEEE Transactions on Electron Devices. 49:1761-1767
We report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen forms hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e08d40515d300371bcab498a92d68e8
https://doi.org/10.1109/ted.2002.803640
https://doi.org/10.1109/ted.2002.803640
Autor:
Toru Tatsumi, Koji Watanabe, T. Fukai, M. Terai, Tohru Mogami, Toyoji Yamamoto, Mitsuhiro Togo
Publikováno v:
IEEE Transactions on Electron Devices. 49:1736-1741
We have demonstrated that oxynitridation using radical-oxygen (radical-O) and radical-nitrogen (radical-N) improves reverse narrow channel effects (RNCE) and reliability in sub-1.5-nm-thick gate-SiO/sub 2/ FETs with narrow channel and shallow-trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35e58fd778b50ec435b7a8b54c4a931d
https://doi.org/10.1109/ted.2002.802634
https://doi.org/10.1109/ted.2002.802634
Publikováno v:
IEEE Transactions on Electron Devices. 49:295-300
Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 /spl Omega//sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by large grain size tungsten on an amorphou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6884c91e168aa61f3a2d809d238843b
https://doi.org/10.1109/16.981220
https://doi.org/10.1109/16.981220
Publikováno v:
IEEE Transactions on Electron Devices. 46:921-926
The bias temperature instability in surface-channel p/sup +/ polysilicon gate p-MOSFETs was evaluated. It was found that a large negative threshold voltage shift (/spl Delta/V/sub th,BT/) is induced by negative bias temperature (BT) stress in short-c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bb05f4c9d7e5e85ac6cb4456f43fd41
https://doi.org/10.1109/16.760398
https://doi.org/10.1109/16.760398
Publikováno v:
Microelectronic Engineering. 30:415-418
Nanometer electron beam lithography has been used for fabrication of sub-0.1 μm MOSFETs. Chemically amplified resist as a single layer mask showed high resolution by optimizing the resist process. Proximity effect correction was applied and showed a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb19c5d48046f8786b3692c6303860ec
https://doi.org/10.1016/0167-9317(95)00276-6
https://doi.org/10.1016/0167-9317(95)00276-6
Autor:
Kiyoshi Takeuchi, Shoko Manako, Jun-ichi Fujita, Toyoji Yamamoto, Seiji Samukawa, Yukinori Ochiai
Publikováno v:
Journal of Photopolymer Science and Technology. 9:715-722
A nanometer electron beam lithography system has been developed and used for fabricating sub-0.1μm gate MOSFETs. The system uses a Zr/O/W thermal field emitter (TFE) and has a 5-nm- diameter beam at a current of 100pA, and an acceleration voltage of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1962a6c14bb27855e90477eb0b3d38f1
https://doi.org/10.2494/photopolymer.9.715
https://doi.org/10.2494/photopolymer.9.715