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Autor:
Toshiyuki Syo, Hisao Yoshimura, Toshiki Kanamoto, Masaru Ito, Shigetaka Kumashiro, Kenta Yamada, Tatsuya Kunikiyo
Publikováno v:
IEICE Transactions on Electronics. :1349-1358
Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practical