Zobrazeno 1 - 10
of 71
pro vyhledávání: '"Toshiyuki Okayasu"'
Autor:
Fumiki Hosoi, Atsushi Ono, T. Inoue, Yusuke Hayase, Daisuke Watanabe, T. Shirai, Toshiyuki Okayasu, T. Akiyama, Masashi Shibata, K. Ueno
Publikováno v:
Journal of Lightwave Technology. 22:2064-2082
A protocol-free parallel optical interconnecting module is introduced as a solution to solve memory test system transmission bottlenecks. The optical transmission system flexibly suited for a memory test system is reviewed and discussed. A parallel o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6c4996259bf8a7ab4a4a1109cf3cab4
https://doi.org/10.1109/jlt.2004.833253
https://doi.org/10.1109/jlt.2004.833253
Autor:
Atsushi Seki, Shin Masuda, Atsushi Ono, Daisuke Watanabe, Toshiyuki Okayasu, Hideo Hara, Tsuyoshi Ataka
Publikováno v:
ITC
To enable high-volume testing of LSIs with high-speed optical and electrical interfaces, we developed a proof-of-concept device of an optical LSI test system for use in mass-production testing. Key technologies include high-density and high-performan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1370aab03f0cf8d92c6553d5cdebc46c
https://doi.org/10.1109/test.2013.6651887
https://doi.org/10.1109/test.2013.6651887
Publikováno v:
ITC
This paper proposes a method for testing a device with multi-level signal interfaces. This method utilizes multi-level drivers that generate multi-level signals and multi-level comparators that are based on a new concept. The multi-level drivers can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2856cfb295f96aeedd23c5d864be1092
https://doi.org/10.1109/test.2012.6401524
https://doi.org/10.1109/test.2012.6401524
Autor:
Tasuku Fujibe, Masakatsu Suda, Kazuhiro Yamamoto, Kazuhiro Fujita, Toshiyuki Okayasu, Y. Nagata, Daisuke Watanabe
Publikováno v:
ITC
A dynamic arbitrary jitter injection method that can be integrated into our high speed and high density CMOS timing generator has been developed. This method makes it possible to inject arbitrary jitter including Periodic Jitter, Random Jitter and Da
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c0bc64cea27929e8b1de8477431b4018
https://doi.org/10.1109/test.2009.5355735
https://doi.org/10.1109/test.2009.5355735
Publikováno v:
ISSCC
Data communication over 300m of distance, such as Ethernet standards, where the required data rate per channel reaches 10Gb/s or more, demand optical transmission [1]. Vertical-cavity surface-emitting laser (VCSEL) and multimode optical fiber (MMF) a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0d25e48ba51e50f38df07527b20ce9e
https://doi.org/10.1109/isscc.2009.4977330
https://doi.org/10.1109/isscc.2009.4977330
Publikováno v:
2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.
An on-chip data jitter measurement circuit in 0.11-mum CMOS is demonstrated. It utilizes a data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The circuit outputs a data jitter waveform in real-time, and doesn't
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43d95cc13894eb6b1d1054a0bde2c077
https://doi.org/10.1109/rfic.2007.380898
https://doi.org/10.1109/rfic.2007.380898
Publikováno v:
ITC
This paper presents solutions to reduce measurement error and test time in an AC characteristic test of a source-synchronous device. In order to realize such a solution, we developed a multi strobe circuit which detects a phase difference between out
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68c9b1425aa5efd567e32acac4c14183
https://doi.org/10.1109/test.2006.297711
https://doi.org/10.1109/test.2006.297711
Autor:
Takehiko Nomura, Toshiyuki Okayasu, Yusuke Hayase, Hajime Mori, Atsushi Ono, Daisuke Watanabe
Publikováno v:
SPIE Proceedings.
High-density parallel optical interconnection is introduced as a solution to solve transmission bottlenecks in memory test system. A protocol-free parallel optical module capable of transmitting from DC to 34.1 Gbps (4.267 Gbps × 8 ch) has been deve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36e3e4c947085e9bd1b176b06fe4f3e0
https://doi.org/10.1117/12.650091
https://doi.org/10.1117/12.650091
Autor:
Satoshi Sudou, Toshiyuki Okayasu, Kazuhiro Yamamoto, Masakatsu Suda, S. Kantake, Daisuke Watanabe
Publikováno v:
ITC
This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3b0cfb2b14e00ce39977aba04581d74
https://doi.org/10.1109/test.2005.1584050
https://doi.org/10.1109/test.2005.1584050
Autor:
Daisuke Watanabe, Kazuhiro Yamamoto, S. Kantake, Masakatsu Suda, Satoshi Sudou, Toshiyuki Okayasu
Publikováno v:
ISSCC
A high-speed high-precision dynamic arbitrary timing generator, fabricated in a 0.18mum CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating frequency of 1.066 and 4.266GHz (multiplexed mode), a timing resolution
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c37f90170fbc7ba4331c882e249ab98
https://doi.org/10.1109/isscc.2006.1696272
https://doi.org/10.1109/isscc.2006.1696272