Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Toshiro Akino"'
Autor:
Takeharu Goji Etoh, Dao Vu Truong Son, Toshiaki Koike Akino, Toshiro Akino, Kenji Nishi, Masatoshi Kureta, Masatoshi Arai
Publikováno v:
Sensors, Vol 10, Iss 4, Pp 4100-4113 (2010)
Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed imag
Externí odkaz:
https://doaj.org/article/c40ce3031aaf4278b77897e316c7cd47
Autor:
Dao Vu Truong Son, Takeharu Goji Etoh, Masatoshi Tanaka, Nguyen Hoang Dung, Vo Le Cuong, Kohsei Takehara, Toshiro Akino, Kenji Nishi, Hitoshi Aoki, Junichi Nakai
Publikováno v:
Sensors, Vol 10, Iss 1, Pp 16-35 (2009)
Our experiencein the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limit
Externí odkaz:
https://doaj.org/article/6b91bc98fcd145c597cf9d963b8be972
Autor:
Toshiro Akino, Masatoshi Arai, Dao Vu Truong Son, Takeharu Etoh, Masatoshi Kureta, Kenji Nishi, Toshiaki Akino
Publikováno v:
Sensors (Basel, Switzerland)
Sensors, Vol 10, Iss 4, Pp 4100-4113 (2010)
Sensors
Volume 10
Issue 4
Pages 4100-4113
Sensors, Vol 10, Iss 4, Pp 4100-4113 (2010)
Sensors
Volume 10
Issue 4
Pages 4100-4113
Averaging of accumulated data is a standard technique applied to processing data with low signal-to-noise ratios (SNR), such as image signals captured in ultra-high-speed imaging. The authors propose an architecture layout of an ultra-high-speed imag
Autor:
Junichi Nakai, Takeharu Etoh, Vo Le Cuong, Kohsei Takehara, Vu Truong Son Dao, Masatoshi Tanaka, Kenji Nishi, H. D. Nguyen, Toshiro Akino, Hitoshi Aoki
Publikováno v:
Sensors, Vol 10, Iss 1, Pp 16-35 (2009)
Sensors (Basel, Switzerland)
Sensors (Basel, Switzerland)
Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limi
Autor:
Toshiro Akino, Tsutomu Honma
Publikováno v:
Bioscience, Biotechnology, and Biochemistry. 62:1684-1687
Five microbial strains that removed hydrogen sulfide (H2S) or methylmercaptan (CH3SH) gas were newly isolated from soil samples. Strain DO-1, one of the isolates, was identified as a member of Pseudomonas sp., and it's immobilized cells removed 1 or
Publikováno v:
Nippon Eiyo Shokuryo Gakkaishi. 45:417-422
好アルカリ性微生物が産生するβ-マンナナーゼを用いて難消化性, 高粘性食物繊維グアガムを部分水解して得た新規な低分子, 低粘性グアガム (GSF) について種々の糖質負荷後の血糖上昇
Autor:
T. Arai, Kousei Takehara, Hirotaka Maruyama, Toshiro Akino, Vu Truong Son Dao, Takeharu Etoh, K. Nishi, H. D. Nguyen, Cuong Vo Le, K. Kitamura
Publikováno v:
SPIE Proceedings.
A feasibility study is presented for an image sensor capable of image capturing at 100 Mega-frames per second (Mfps). The basic structure of the sensor is the backside-illuminated ISIS, the in-situ storage image sensor, with slanted linear CCD memori
Autor:
Takashi Hamahata, Toshiro Akino
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540390947
PATMOS
PATMOS
A new operation mode for a lateral unified-complementary BiCMOS (hereafter abbreviated as U-CBiCMOS) buffer driver based on a partially depleted CMOS/SOI process is proposed. The scheme utilizes a gated npn or pnp BJT inherent to a n- or p-channel MO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14c70be933b853a55b0860b2f360a30c
https://doi.org/10.1007/11847083_22
https://doi.org/10.1007/11847083_22
Publikováno v:
ISCAS
This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that the concept of a fractal dim
Publikováno v:
ASP-DAC
Proposes a transistor placement algorithm to generate standard cell layout in a 2D placement style that is not restricted to row-based transistor placement. The cost function constructed for transistor placement optimization is able to optimize wirin