Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Toshio Sunaga"'
Publikováno v:
IEEE Transactions on Magnetics. 40:1723-1731
Analytical expressions of minimum electric current and power dissipation, and bit line and word line currents that produce them, for writing data into magnetic tunnel junction (MTJ) magnetoresistive random access memory (MRAM) cells are derived with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a66df15a6d4b55adff3f04c60993fc81
https://doi.org/10.1109/tmag.2004.826628
https://doi.org/10.1109/tmag.2004.826628
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:105-110
A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b17beae1e5e718812ea2ea7677fbdfa
https://doi.org/10.1109/4.553188
https://doi.org/10.1109/4.553188
Autor:
Toshio Sunaga
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:767-772
A DRAM sensing circuit that achieves both a fast RAS access time and a high-bandwidth burst operation is proposed. For the data burst capability of synchronous DRAM's, 256-bit-long data I/O lines are divided into eight segments. A small local latch i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::820a5d4772bc29edd980397d45f715d0
https://doi.org/10.1109/4.509862
https://doi.org/10.1109/4.509862
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1556-1559
A combined DRAM and logic chip has been developed for massively parallel processing (MPP) applications. A trench cell 4-Mb CMOS DRAM technology is used to fabricate the chip with an additional third-level metal layer. The 5-V 0.8-/spl mu/m technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99c30c9b70412b0835b11f223ba47b8a
https://doi.org/10.1109/4.540068
https://doi.org/10.1109/4.540068
Autor:
N. Tanigaki, N. Yamasaki, Y. Mori, K. Kasuya, Hisatada Miyatake, K. Kitamura, Toshio Sunaga, M. Tanaka, T. Saitoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:1006-1014
DRAM macros in 4-Mb (0.8-/spl mu/m) and 16-Mb (0.5-/spl mu/m) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96d5bb62dcb816bd46b5fb5ede41abb0
https://doi.org/10.1109/4.406409
https://doi.org/10.1109/4.406409
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:25-28
A new DRAM sensing approach that uses variable precharge voltage has been developed and analyzed in simulations. It uses a voltage swing only on the bit-line connected to the accessed cell. The bit-line precharge voltage varies from one RAS cycle to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54907c68d2c991085d6b3aac101f4acd
https://doi.org/10.1109/4.350198
https://doi.org/10.1109/4.350198
Publikováno v:
IBM Journal of Research and Development. 39:43-50
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::beb28ac91b2786c2da0b3de1f42c6302
https://doi.org/10.1147/rd.391.0043
https://doi.org/10.1147/rd.391.0043
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:998-1005
A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a61c2f5fdd4d375e20f13aeb12a45f67
https://doi.org/10.1109/4.406399
https://doi.org/10.1109/4.406399
Autor:
Toshio Sunaga
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:1353-1358
A 4-Mb mask ROM in a 256-Kb/spl times/16 organization is described. It is fabricated with a 1.0-/spl mu/m CMOS process, using single polysilicon, two levels of metal, and 3.0/spl times/4.4 /spl mu/m/sup 2/ X-cells. Unlike conventional ROM's, it imple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f738db9366120fdf20aa799c8856abb2
https://doi.org/10.1109/4.328636
https://doi.org/10.1109/4.328636
Autor:
T. Saitoh, Toshio Sunaga, Kohji Hosokawa, S.H. Dhong, Roy Edwin Scheuerlein, Toshiaki Kirihata, A. Satoh, H. Hashimoto, T. Yoshikawa, M. Kazusawa, K. Kitamura, Y. Sakaue, K. Tobimatsu, Yasunao Katayama
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1222-1228
A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7- mu m L/sub eff/ CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm*6.38-mm chip, organized as either 512 K word*8
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e2aaeafac737ad7aa122b3696eaf43
https://doi.org/10.1109/4.149425
https://doi.org/10.1109/4.149425