Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Toshinori Hosokawa"'
Publikováno v:
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
Publikováno v:
IEICE Transactions on Information and Systems. :1023-1030
Publikováno v:
DFT
It is reported that many cell-internal defects remain undetected when VLSI testing is performed using test sets generated for only traditional fault models like stuck-at faults and transition faults. Therefore, test generation methods for cell-aware,
Publikováno v:
IOLTS
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to maintain the high fault efficiency. To solve the challenge, a design-for-testability method using partial scan design and controller augmentation to
Publikováno v:
IOLTS
High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in transition delay fault scan testing, resulting in excessive IR drop. Since excessive IR-drop significantl
Publikováno v:
IEICE Transactions on Information and Systems. :2118-2125
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2824-2833
Autor:
Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai, Masayuki Arai
Publikováno v:
DFT
High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases pa
Publikováno v:
DFT
Recently, it is indispensable to test in transition fault model due to timing defects increase along with complication and high speed of VLSI. However, the transition fault coverage tends to be lower than the stuck-at fault coverage due to untestable
Publikováno v:
IOLTS
With the growing clock frequencies and complexity for VLSIs, transition fault testing is required. However, the number of untestable transition faults is generally much more than that of untestable stuck-at faults due to the circuit structures and fu