Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Toshinari Takayanagi"'
Autor:
V. Mathur, Howard L. Levy, D. Bistry, Bruce Petrick, Ana Sonia Leon, Jinseung Son, Ha Pham, Mandeep Singh, Jinuk Luke Shin, U. Nair, Toshinari Takayanagi, N. Moon, Jeffrey Y. Su
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:7-18
A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two UltraSPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::602dcbf853e5301e4c26da81905b2139
https://doi.org/10.1109/jssc.2004.838023
https://doi.org/10.1109/jssc.2004.838023
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:726-734
A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V/sub TH/) of the transistors is reduced for high performance at l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::028eb461232124dd01083b551c921d91
https://doi.org/10.1109/4.918909
https://doi.org/10.1109/4.918909
Autor:
Yohji Watanabe, Hideho Arakida, N. Machida, Osamu Yamagishi, T. Samata, Tsuyoshi Nishikawa, Tohru Furuyama, M. Takahashi, Shigenobu Minami, Toshihide Fujiyoshi, T. Terazawa, K. Ohmori, J. Shirakura, Asano Atsushi, M. Hamada, Tadahiro Kuroda, Toshinari Takayanagi, Hideaki Yamamoto, Hiroshi Nakamura
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1713-1721
A 240-mW single-chip MPEG-4 videophone LSI with a 16-Mb embedded DRAM is fabricated utilizing a 0.25-/spl mu/m CMOS triple-well quad-metal technology. The videophone LSI is applied to the 3GPP 3G-324M video-telephony standard for IMT-2000, and implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::039c25faf481327101f30fc320ee5d28
https://doi.org/10.1109/4.881219
https://doi.org/10.1109/4.881219
Autor:
Tsukasa Shirotori, Takayasu Sakurai, Sumio Tanaka, Tetsuya Iizuka, Yuichi Miyazawa, Toshinari Takayanagi, Kazutaka Nogami, Kazuhiro Sawada, Masanori Uchida, K. Katoh, Yoichi Hiruta, Kenji Sakaue, Y. Itoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:100-108
A 32-kB cache macro with an experimental reduced instruction set computer (RISC) is realized. A pipelined cache access to realize a cycle time shorter than the cache access time is proposed. A double-word-line architecture combines single-port cells,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76417ccd9d3d6a0fdfee45e214790a21
https://doi.org/10.1109/4.50291
https://doi.org/10.1109/4.50291
Autor:
Zongjian Chen, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Dan Murray, Eric Shiu, Priya Ananthanarayanan, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tam, Pradeep Trivedi, James Wang, Ricky Wen, John Yong, Sukalpa Biswas, Brian Campbell, Hao Chen, Shailendra Desai, Shaishav Desai, Dominic Go, Rajat Goel
Publikováno v:
ISSCC
An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design tec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4d28527a5d5a46ec1de4889bce0cd57
https://doi.org/10.1109/isscc.2007.373609
https://doi.org/10.1109/isscc.2007.373609
Autor:
Toshinari Takayanagi, V. von Kaenel
Publikováno v:
CICC
Implementations of a thermal noise and a chaotic True Random Number Generator (TRNG) are presented. They are embedded in a large commercial SoC and used for cryptographic applications (SSL and key generation). Their outputs are combined to improve th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0999e385591ece523022bd9bfc75bfc
https://doi.org/10.1109/cicc.2007.4405730
https://doi.org/10.1109/cicc.2007.4405730
Publikováno v:
DAC
A processor core, previously implemented in a 0.25 μm AI process, is redesigned for a 0.13 μ m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applicatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::998b79040dd62a5c3d1f50be6dd6553a
https://doi.org/10.1145/996566.996750
https://doi.org/10.1145/996566.996750
Publikováno v:
International Symposium on VLSI Technology, Systems and Applications.
A finely tunable standard cell (FTSC) method is introduced to cope with the complexity and high-speed nature of application-specific memory ICs (ASMICs). The method is applied to an integrated cache memory, a typical high-speed ASMIC, and achieves ad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c27cd729620233a323c383c1f9bfa20
https://doi.org/10.1109/vtsa.1989.68599
https://doi.org/10.1109/vtsa.1989.68599
Autor:
Takayasu Sakurai, B. Maness, N. Hatanaka, S. Purcell, S. Kitabayashi, M. Takahashi, T. Higashi, J. Zheng, J. Thomson, M. Klein, R. Carpenter, L. Tinkey, D. Renfrow, Kazutaka Nogami, Toshinari Takayanagi, Fumitoshi Hatori, J. Battle, R. Donthi, Makoto Ichida
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ee7ffe76c715e807a0d16aeaddd7cf1
https://doi.org/10.1109/isscc.1996.488548
https://doi.org/10.1109/isscc.1996.488548
Autor:
Sumio Tanaka, H. Akiba, K. Minagawa, Nobuyuki Ikumi, Masato Nagamatsu, Yoichi Hiruta, K. Miyamoto, Kazuhiro Sawada, Yoshihisa Kondo, Chandra S. Joshi, P. Rodman, Toshinari Takayanagi, Monica R. Nofal, Man Kit Tang, J. Scanlon, Joe Bratt, P. Hsu
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
A RISC CMOS superscalar microprocessor, operating at 75 MHz, executes up to four instructions per clock cycle, totalling 300M instructions per second. The chip implements a 64 b architecture and includes a 64 b integer pipeline, 16 kB instruction cac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c44890439ebd82fde825a48a1beb97b8
https://doi.org/10.1109/isscc.1994.344669
https://doi.org/10.1109/isscc.1994.344669