Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Toshiki Hisada"'
Autor:
Yasuyuki Kajitani, Kazushige Kanda, Manabu Sato, Takahiro Shimizu, Hiroshi Sugawara, Junji Musha, Yee Lih Koh, Tomoki Nakagawa, Kazuaki Kawaguchi, Takahiro Sugimoto, Koji Hosono, Jumpei Sato, Mario Sako, Yusuke Ochi, Tomoaki Nakano, Katsuaki Sakurai, Ryo Fukuda, Ryoichi Tachibana, Naoki Kobayashi, Juan Lee, Hiroki Date, Hiroaki Nasu, Koichi Kawakami, Makoto Miakashi, Dai Nakamura, Yuuki Matsumoto, Jieyun Zhou, Shuo Chen, Tadashi Someya, Hiroshi Nakamura, Kosuke Yanagidaira, Namasivayam Raghunathan, Takeshi Ogawa, M. Kojima, Masami Masuda, Toshifumi Hashimoto, Jun Nakai, Takahisa Kawabe, Taira Shibuya, Masatsugu Ogawa, Osamu Nagao, Takahiro Yamashita, Teruo Takagiwa, Toshiki Hisada, Tomoharu Hashiguchi, Yasushi Nagadomi, Mizuki Uda, Noboru Shibata, Takatoshi Minamoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:178-188
A 1.33-Tb 4-bit/cell quadruple-level (QLC) 3-D flash memory in a 96-word-line (WL)-layer technology that achieves 8.5 Gb/mm2 has been developed. This is the biggest capacity and the highest bit density ever reported. A source-bias-negative-sense with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79bedba3ba6edf399921f1719678c350
https://doi.org/10.1109/jssc.2019.2941758
https://doi.org/10.1109/jssc.2019.2941758
Autor:
J. Zhou, Teruo Takagiwa, Toshifumi Hashimoto, Y. Ochi, Toshiki Hisada, Mario Sako, Takahiro Yamashita, M. Uda, Takatoshi Minamoto, Hiroshi Sugawara, T. Kawabe, Noboru Shibata, N. Raghunathan, Junichi Sato, Koji Hosono, Osamu Nagao, T. Ogawa, Naoki Kobayashi, T. Someya, Shuo Chen, Ryo Fukuda, Koichi Kawakami, H. Date, Makoto Miakashi, Y. Matsumoto, Takahiro Shimizu, M. Sato, J. Nakai, Naohito Morozumi, M. Ogawa, Tomoharu Hashiguchi, Tomohiro Sugimoto, H. Takamoto, T. Nakano, T. Nakagawa, Masami Masuda, T. Shibuya, M. Kojima, Hiroshi Nakamura, H. Nasu, Kosuke Yanagidaira, Kiyofumi Sakurai, Yasushi Nagadomi, Kazuaki Kawaguchi, Yasuyuki Kajitani, Kazushige Kanda, Junji Musha, Ryoichi Tachibana, T. Kaneko, Y. L. Koh, Juan Lee, Dai Nakamura
Publikováno v:
ISSCC
Since 3D-Flash memory took over for 2D-Flash memory, chip capacity has continuously improved [1]–[3]. In the 2D-Flash era, 2b/cell (MLC) offered higher performance and reliability, while a 3b/cell (TLC) offered the lowest cost. Thanks to a larger f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::393ff9436b178f29b8711c1023ffae82
https://doi.org/10.1109/isscc.2019.8662443
https://doi.org/10.1109/isscc.2019.8662443
Autor:
Hua-Ling Hsu, Hiromitsu Komai, Minoru Yamashita, Tai-yuan Tseng, Kapil Verma, Yasuyuki Kajitani, Hiroshi Nakamura, Venky Ramachandra, Jang Yong Kang, Pai K. Manjunath, Siddhesh Darne, Noboru Shibata, Jong Yuh, Chang Siau, Heguang Li, Raghavendra Rachineni, Toshiki Hisada, Katsuaki Isobe, Steve Choi, Toru Miwa, Takatoshi Minamoto, Naoya Tokiwa, Naoki Ookuma, Koichiro Hayashi, Alex Yap, Anirudh Amarnath, Susumu Ozawa, Masatoshi Okumura, Swaroop Kulkani, Stanley Jeong, Hitoshi Miwa, Tomoo Hishida, Jason Li, Pradeep Anantula, Masaki Unno, Hardwell Chibvongodze, Kazuaki Kawaguchi, Aki Matsuda, Ohwon Kwon, Masashi Yamaoka, Kwang-Ho Kim, Muralikrishna Balaga, Qui Nguyen, Takuya Ariki, Lei Lin, Anil Pai, Masahito Takehara, Ryo Fukuda, Mitsuyuki Watanabe, Srinivas Rajendra, Seungpil Lee, Yosuke Kato
Publikováno v:
ISSCC
Advancements in 3D-Flash memory-layer-stacking technology has enabled density scaling that circumvents the lithography limitations which have prevented 2D-NAND Flash memory from scaling [1]. Bit densities as high as 5.95Gb/mm2 on a single die were re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::244704105131d64a13561260e586aa32
https://doi.org/10.1109/isscc.2019.8662445
https://doi.org/10.1109/isscc.2019.8662445
Autor:
Katsuaki Sakurai, Feng Lu, Kenro Kubota, Hiroshi Sugawara, Yoshihiko Shindo, Steve Choi, Junji Musha, Yusuke Ochi, Hao Nguyen, Hiroshi Nakamura, Yee Koh, Yasuhiro Suematsu, Ryo Fukuda, Tomoko Nishiuchi, Spiros Georgakis, Keyur Payak, Masatsugu Kojima, Sanad Bushnaq, Naoki Kobayashi, Kwang-ho Kim, Hiroe Minagawa, Manabu Sato, Yuuki Shimizu, Naoaki Kanagawa, Susumu Fujimura, Teruo Takagiwa, Kenichi Abe, Takahiro Shimizu, Toshiki Hisada, Taichi Wakui, Hiroshi Maejima, Susumu Ozawa, Makoto Miakashi, Srinivas Rajendra, Kazushige Kanda, Hiroshi Yoshihara, Namas Raghunathan, Akihiro Imamoto, Koji Hosono, Dong He, Satoshi Inoue, Masatsugu Ogawa, Seungpil Lee, Jumpei Sato, Fumihiro Kono, Yuui Shimizu, Kazuhiko Satou, Takuya Futatsuyama, Venky Ramachandra, Naohito Morozumi, Weihan Wang, Tomoharu Hashiguchi, Hicham Haibi, Noboru Shibata, Takatoshi Minamoto, Xu Li, Kouichirou Yamaguchi, Toshifumi Hashimoto, Takahiro Yamashita, Ken Cheah, Mitsuhiro Abe, Tetsuya Kaneko, Tadashi Yasufuku, Takahiro Sugimoto
Publikováno v:
ISSCC
The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97bbed59d5735369bb77aa3c73309af7
https://doi.org/10.1109/isscc.2018.8310321
https://doi.org/10.1109/isscc.2018.8310321
Autor:
Hong Ding, T. Pham, Takahiro Shimizu, Junji Musha, H. Nasu, T. Ogawa, Naoki Kobayashi, Toshiki Hisada, N. Ookuma, Noboru Shibata, G. Hemink, M. Sato, Toshifumi Hashimoto, S. Sakai, K. Kanazawa, Masahiro Yoshihara, Yosuke Kato, Yasuyuki Kajitani, Tomofumi Fujimura, Kazushige Kanda, Tomohiro Sugimoto, G. Liang, Y. Matsumoto, Katsuaki Isobe, K. Iwasa, T. Kobayashi, J. Nakai, M. Inagaki, S. Inoue, T. Ariki, Masaru Koyanagi, M. Watanabe, K. Inuzuka, Yoshinao Suzuki, Naofumi Abiko, M. Kojima, Naoaki Kanagawa, Y. Honda, Y. Utsunomiya, S. Zaitsu, Makoto Miakashi, Mitsuhiro Noguchi, M. Higashitani, D. He, F. Moogat, Hardwell Chibvongodze, Mitsuaki Honma, Teruhiko Kamei, Yuui Shimizu, Cuong Trinh, K. Ino, Michio Nakagawa, Toshihiro Suzuki, Ryuji Yamashita
Publikováno v:
ISSCC
NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b3bcf4af4f8a6be127d825af6311ce6
https://doi.org/10.1109/jssc.2012.2215094
https://doi.org/10.1109/jssc.2012.2215094
Autor:
Norifumi Kajimura, H. Otake, F. Ito, Kazushige Kanda, Y. Okukawa, Teruhiko Kamei, Mitsuhiro Noguchi, M. Higashitani, M. Kojima, Masahiro Yoshihara, Kazuhide Yoneya, Frank Tsai, Masanobu Shirakawa, M. Itoh, Siu Lung Chan, Toshiki Hisada, Yosuke Kato, Takashi Taira, Eiichi Makino, Binh Quang Le, Dai Nakamura, G. Hemink, Toshio Yamamura, Alex Mak, Shinji Miyamoto, Raul-Adrian Cernea, Yoshinao Suzuki, Shigeo Ohshima, Susumu Fujimura, Koji Hosono, Toru Miwa, Yoshiaki Takeuchi, T. Maruyama, T. Arizono, Toshitake Yaegashi, Masaru Koyanagi, K. Ino
Publikováno v:
ISSCC
NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9da534784a76ae16b8a2968acd297f0f
https://doi.org/10.1109/isscc.2008.4523241
https://doi.org/10.1109/isscc.2008.4523241
Publikováno v:
ACM Transactions on Architecture & Code Optimization; Mar2024, Vol. 21 Issue 1, p1-26, 26p
Publikováno v:
ACM Transactions on Embedded Computing Systems; Jan2023, Vol. 22 Issue 1, p1-32, 32p
Autor:
Shibata, Noboru, Kawabe, Takahisa, Shibuya, Taira, Sako, Mario, Yanagidaira, Kosuke, Hashimoto, Toshifumi, Date, Hiroki, Sato, Manabu, Nakagawa, Tomoki, Musha, Junji, Minamoto, Takatoshi, Kanda, Kazushige, Uda, Mizuki, Nakamura, Dai, Sakurai, Katsuaki, Yamashita, Takahiro, Zhou, Jieyun, Tachibana, Ryoichi, Takagiwa, Teruo, Sugimoto, Takahiro
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2020, Vol. 55 Issue 1, p178-188, 11p
A 19 nm 112.8 mm^2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface.
Autor:
Kanda, Kazushige, Shibata, Noboru, Hisada, Toshiki, Isobe, Katsuaki, Sato, Manabu, Shimizu, Yui, Shimizu, Takahiro, Sugimoto, Takahiro, Kobayashi, Tomohiro, Kanagawa, Naoaki, Kajitani, Yasuyuki, Ogawa, Takeshi, Iwasa, Kiyoaki, Kojima, Masatsugu, Suzuki, Toshihiro, Suzuki, Yuya, Sakai, Shintaro, Fujimura, Tomofumi, Utsunomiya, Yuko, Hashimoto, Toshifumi
Publikováno v:
IEEE Journal of Solid-State Circuits; Jan2013, Vol. 48 Issue 1, p159-167, 9p