Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Toshiaki Menjo"'
Publikováno v:
2022 IEEE 39th International Electronics Manufacturing Technology Conference (IEMT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ceffe1e22e416900dbefd3df4a71bb8
https://doi.org/10.1109/iemt55343.2022.9969504
https://doi.org/10.1109/iemt55343.2022.9969504
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
This paper reports on a novel chip placement technology for Fan-out WLP using expansion technology and self-assembly technique. In a preceding paper, we reported that we have developed the novel tape expansion machine which can expand the tape in fou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fdf5b4b54fab47596da4010fa58a2d5
https://doi.org/10.1109/ectc32696.2021.00178
https://doi.org/10.1109/ectc32696.2021.00178
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
This paper describes the results of novel stress-strain curve measuring method for high expansion tape. We previously reported that we have developed the novel tape expansion machine with a new function allowing that tapes can be expanded in four dir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c27e21ef789b5a1c95aa7e7c6cbc8efc
https://doi.org/10.1109/ectc32862.2020.00171
https://doi.org/10.1109/ectc32862.2020.00171
Publikováno v:
3DIC
This paper repots on a novel pick-up and place process for FO-WLP using high expansion tape and tape expansion machine device. We previously reported that we have developed the novel tape expansion machine with a new function allowing that tapes can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78816d2b496eaa1658cb151f72dd6a1c
https://doi.org/10.1109/3dic48104.2019.9058827
https://doi.org/10.1109/3dic48104.2019.9058827
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Wafer Level Package (WLP) is a packaging technology focusing on IC packaging at wafer level instead of chip level. Conventional WLPs are designed for fan-in chip scale packaging but the shrinkage of pad pitch and size at the chip to package interface
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11231d0322fba250e41b8eb6c46c7cdb
https://doi.org/10.1109/ectc.2017.112
https://doi.org/10.1109/ectc.2017.112
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55f1a20b2220206dbd6ca64bf0be0072
https://doi.org/10.1109/ectc.2017.76
https://doi.org/10.1109/ectc.2017.76