Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Tonmoy Dhar"'
Autor:
Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven Burns, Ramesh Harjani, Sachin S. Sapatnekar
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).
Autor:
Steven M. Burns, Hao Chen, Tonmoy Dhar, Ramesh Harjani, Jiang Hu, Nibedita Karmokar, Kishor Kunal, Yaguang Li, Yishuang Lin, Mingjie Liu, Meghna Madhusudan, Parijat Mukherjee, David Z. Pan, Jitesh Poojary, S. Ramprasath, Sachin S. Sapatnekar, Arvind K. Sharma, Wenbin Xu, Soner Yaldiz, Keren Zhu
Publikováno v:
Machine Learning Applications in Electronic Design Automation ISBN: 9783031130731
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eab3ee9e6bd1f2e4c966eae63911c8a6
https://doi.org/10.1007/978-3-031-13074-8_17
https://doi.org/10.1007/978-3-031-13074-8_17
Publikováno v:
Microelectronics Reliability. 142:114912
Autor:
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. :1-1
Publikováno v:
IRPS
This paper illustrates the impact of temporal degradations due to aging on current digital-to-analog converters (IDACs) within the context of a feed-forward equalizer (FFE) that is used in high-speed links. Aging causes mismatch in the current mirror
Autor:
Jiang Hu, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Yaguang Li, Tonmoy Dhar, Arvind Sharma, Susmita Dey Manasi, Sachin S. Sapatnekar, Kishor Kunal
Publikováno v:
ASP-DAC
Placement algorithms for analog circuits explore numerous layout configurations in their iterative search. To steer these engines towards layouts that meet the electrical constraints on the design, this work develops a fast feasibility predictor to g
Autor:
Soner Yaldiz, Kishor Kunal, Arvind Sharma, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar, Tonmoy Dhar, Yaguang Li, Steven M. Burns, Jiang Hu, Yishuang Lin, Jitesh Poojary, Parijat Mukherjee
Publikováno v:
ICCAD
The ALIGN (Analog Layout, Intelligently Generated from Netlists) project attempts to remedy these limitations using a variety of strategies: (a) it recognizes geometric constraints and subcircuits through automated circuit recognition and annotation;
Autor:
Jitesh Poojary, Kishor Kunal, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar, Tonmoy Dhar
Publikováno v:
ICCAD
Analog layout synthesis requires some elements in the circuit netlist to be matched and placed symmetrically. However, the set of symmetries is very circuit-specific and a versatile algorithm, applicable to a broad variety of circuits, has been elusi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fcf22fd0331682da4145440de7ceee4b
http://arxiv.org/abs/2010.00051
http://arxiv.org/abs/2010.00051
Autor:
Kishor Kunal, Ramesh Harjani, Jiang Hu, Sachin S. Sapatnekar, Arvind Sharma, Wenbin Xu, Jitesh Poojary, Yaguang Li, Tonmoy Dhar, Parijat Mukherjee, Meghna Madhusudan, Steven M. Burns
Publikováno v:
ISPD
The problem of analog design automation has vexed several generations of researchers in electronic design automation. At its core, the difficulty of the problem is related to the fact that machinegenerated designs have been unable to match the qualit
Autor:
Sachin S. Sapatnekar, Tonmoy Dhar
Publikováno v:
IRPS
This paper studies the impact of hot carrier injection and bias temperature instability on a mixed-signal delay locked loop, at the block and system levels. Aging affects delays on the reset line of the phase detector, degrading sensitivity to input