Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Tomoya Sugiura"'
Autor:
Takahiro Kinoshita, Takashi Kawakami, Kenichi Yamazaki, Tsutomu Matsuda, Tomoya Sugiura, Naohiro Furukawa
Publikováno v:
The Proceedings of the Materials and Mechanics Conference. 2015:GS0111-26
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::146d6e50707840071f5bc26b7fa5809f
https://doi.org/10.1299/jsmemm.2015._gs0111-26
https://doi.org/10.1299/jsmemm.2015._gs0111-26
Autor:
Yasumitsu Orii, Takashi Kawakami, Takahiro Kinoshita, Sayuri Kohara, Keiji Matsumoto, Tomoya Sugiura
Publikováno v:
Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales.
3D packaging technology and TSV (Through Silicon Via) technology have been developed to reduce size and improve performance of semiconductor devices. On the other hand, cooling performance is decreased because thermal sources are accumulated and conc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e646187b619c4d91bcc939b3621eb5a
https://doi.org/10.1115/ipack2015-48142
https://doi.org/10.1115/ipack2015-48142
Autor:
Yasumitsu Orii, Takashi Kawakami, Tomoya Sugiura, Keiji Matsumoto, Takahiro Kinoshita, Sayuri Kohara
Publikováno v:
2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54eb214fe94012ca64598425f218aaff
https://doi.org/10.1109/impact.2014.7048369
https://doi.org/10.1109/impact.2014.7048369
Autor:
Tomoya Sugiura, Takahiro Kinoshita, Takashi Kawakami, Yasumitsu Orii, Sayuri Kohara, Keiji Matsumoto
Publikováno v:
2014 9th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
In conventional SiP (System in Package), several semiconductor chips had been 2D arranged in an interposer and a mother board. However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4f7ed3670926639a7a8f4ecf850eb6f
https://doi.org/10.1109/impact.2014.7048370
https://doi.org/10.1109/impact.2014.7048370
Autor:
Tomoya Sugiura, Takashi Kawakami, Sayuri Kohara, Keiji Matsumoto, Takahiro Kinoshita, Yasumitsu Orii
Publikováno v:
2014 International Conference on Electronics Packaging (ICEP).
Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using FEM (Finite Element Method). In case of the condition of device operation, equivalent st
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc79068a2fabf61ebab559e95d82c00a
https://doi.org/10.1109/icep.2014.6826670
https://doi.org/10.1109/icep.2014.6826670
Autor:
Takashi Kawakami, Tomoya Sugiura, Takahiro Kinoshita, Keiji Matsumoto, Yasumitsu Orii, Sayuri Kohara
Publikováno v:
2014 International Conference on Electronics Packaging (ICEP).
The stresses of TSV (Through Silicon Via) and Si chips in 3D-SiP were discussed with a large scale simulator based on FEM (Finite Element Method), ADVENTURECluster. In this study, the stacked layer structure of Si chips is modeled accurately. Thermal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b6fec6260abdfd533c81d0b6371d6d6
https://doi.org/10.1109/icep.2014.6826671
https://doi.org/10.1109/icep.2014.6826671